Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver. - Chengzhi Pan; Nader Bagherzadeh; Amir Hosein Kamalizad; Arezou Koohi (DATE, 2003)

Fast Parallel FFT on a Reconfigurable Computation Platform. - Amir Hosein Kamalizad; Chengzhi Pan; Nader Bagherzadeh (SBAC-PAD, 2003)

MaRS: a macro-pipelined reconfigurable system. - Nozar Tabrizi; Nader Bagherzadeh; Amir Hosein Kamalizad; Haitao Du (Conf. Computing Frontiers, 2004)

Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform. - Amir Hosein Kamalizad; Richard Plettner; Chengzhi Pan; Nader Bagherzadeh (SoCC, 2004)

A Programmable DSP Architecture for Wireless Communication Systems. - Amir Hosein Kamalizad; Nozar Tabrizi; Nader Bagherzadeh; Akira Hatanaka (ASAP, 2005)

A Reconfigurable Architecture for Wireless Communication Systems. - Hooman Parizi; Afshin Niktash; Amir Hosein Kamalizad; Nader Bagherzadeh (ITNG, 2006)

RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding. - Afshin Niktash; Hooman Parizi; Amir Hosein Kamalizad; Nader Bagherzadeh (WCNC, 2008)