Reversible Implementation of Densely-Packed-Decimal Converter to and from Binary-Coded-Decimal Format Using in IEEE-754R. - Amir Kaivani; Ali Zakerolhosseini; Saeid Gorgin 001; Mahmood Fazlali (ICIT, 2006)

Reversible Barrel Shifters. - Saeid Gorgin 001; Amir Kaivani (AICCSA, 2007)

Binary-coded decimal digit multipliers. - Ghassem Jaberipur; Amir Kaivani (IET Comput. Digit. Tech., 2007)

Improving the Speed of Parallel Decimal Multiplication. - Ghassem Jaberipur; Amir Kaivani (IEEE Trans. Computers, 2009)

Fully redundant decimal addition and subtraction using stored-unibit encoding. - Amir Kaivani; Ghassem Jaberipur (Integr., 2010)

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture. - Amir Kaivani; Ghassem Jaberipur (Comput. J., 2011)

Improving the speed of decimal division. - Amir Kaivani; Adel Hosseiny; Ghassem Jaberipur (IET Comput. Digit. Tech., 2011)

High-frequency sequential decimal multipliers. - Amir Kaivani; Li Chen; Seok-Bum Ko (ISCAS, 2012)

Decimal signed digit addition using stored transfer encoding. - Amir Kaivani; Seok-Bum Ko (CCECE, 2013)

Decimal SRT Square Root: Algorithm and Architecture. - Amir Kaivani; Seok-Bum Ko (Circuits Syst. Signal Process., 2013)

Decimal Division Algorithms: The Issue of Partial Remainders. - Amir Kaivani; Seok-Bum Ko (J. Signal Process. Syst., 2013)

High-speed FFT processors based on redundant number systems. - Amir Kaivani; Seok-Bum Ko (ISCAS, 2014)

Area Efficient Sequential Decimal Fixed-point Multiplier. - Liu Han; Amir Kaivani; Seok-Bum Ko (J. Signal Process. Syst., 2014)

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation. - Amir Kaivani; Seok-Bum Ko (IEEE Trans. Very Large Scale Integr. Syst., 2016)