DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. - Saaed S. Faraji; Javad Talafy; Amir M. Hajisadeghi; Hamid R. Zarandi (DSD, 2018)

MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits. - Amir M. Hajisadeghi; Hossein Bardareh; Hamid R. Zarandi (DSD, 2018)

A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays. - Hossein Bardareh; Amir M. Hajisadeghi; Hamid R. Zarandi (IOLTS, 2018)

A Fast and Efficient Fault Tree Analysis Using Approximate Computing. - Salar Hashemi; Amir M. Hajisadeghi; Hamid R. Zarandi; Saadat Pour-Mozafari (EDCC, 2019)

DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. - Saeed Seyedfaraji; Amir M. Hajisadeghi; Javad Talafy; Hamid R. Zarandi (Microprocess. Microsystems, 2020)

CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics. - Amir M. Hajisadeghi; Hamid R. Zarandi (Microprocess. Microsystems, 2021)

EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis. - Salar Hashemi; Amir M. Hajisadeghi; Hamid R. Zarandi (DSD, 2022)

ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks. - Ali Sedaghatgoo; Amir M. Hajisadeghi; Mahmoud Momtazpour; Nader Bagherzadeh (CoRR, 2024)

Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM. - Amir M. Hajisadeghi; Hamid R. Zarandi; Mahmoud Momtazpour (CoRR, 2024)

Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM. - Amir M. Hajisadeghi; Mahmoud Momtazpour; Hamid R. Zarandi (Future Gener. Comput. Syst., 2024)

OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits. - Maryam Ghane; Amir M. Hajisadeghi; Hamid R. Zarandi (CoRR, 2025)