An assertion-based verification methodology for system-level design. - Amir Masoud Gharehbaghi; Benyamin Hamdin Yaran; Shaahin Hessabi; Maziar Goudarzi (Comput. Electr. Eng., 2007)

System-Level Assertion-Based Performance Verification for Embedded Systems. - Hassan Hatefi-Ardakani; Amir Masoud Gharehbaghi; Shaahin Hessabi (CSICC, 2008)

Timing verification of distributed network systems at higher levels of abstraction. - Hassan Hatefi-Ardakani; Amir Masoud Gharehbaghi; Shaahin Hessabi (HLDVT, 2008)

Debugging from high level down to gate level. - Masahiro Fujita; Yoshihisa Kojima; Amir Masoud Gharehbaghi (DAC, 2009)

Transaction-based debugging of system-on-chips with patterns. - Amir Masoud Gharehbaghi; Masahiro Fujita (ICCD, 2009)

Pipelined Microprocessors Optimization and Debugging. - Bijan Alizadeh; Amir Masoud Gharehbaghi; Masahiro Fujita (ARC, 2010)

Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only). - Amir Masoud Gharehbaghi; Bijan Alizadeh; Masahiro Fujita (FPGA, 2010)

Formal verification guided automatic design error diagnosis and correction of complex processors. - Amir Masoud Gharehbaghi; Masahiro Fujita (HLDVT, 2011)

Global transaction ordering in Network-on-Chips for post-silicon validation. - Amir Masoud Gharehbaghi; Masahiro Fujita (ISQED, 2011)

Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods. - Amir Masoud Gharehbaghi; Masahiro Fujita (Asian Test Symposium, 2012)

Automatic rectification of design errors in complex processors with programmable hardware. - Amir Masoud Gharehbaghi; Masahiro Fujita (FPT, 2012)

Transaction-based post-silicon debug of many-core System-on-Chips. - Amir Masoud Gharehbaghi; Masahiro Fujita (ISQED, 2012)

Transaction Ordering in Network-on-Chips for Post-Silicon Validation. - Amir Masoud Gharehbaghi; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Rectification of advanced microprocessors without changing routing on FPGAs (abstract only). - Satoshi Jo; Amir Masoud Gharehbaghi; Takeshi Matsumoto; Masahiro Fujita (FPGA, 2013)

Debugging processors with advanced features by reprogramming LUTs on FPGA. - Satoshi Jo; Amir Masoud Gharehbaghi; Takeshi Matsumoto; Masahiro Fujita (FPT, 2013)

Specification and formal verification of power gating in processors. - Amir Masoud Gharehbaghi; Masahiro Fujita (ISQED, 2014)

Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model. - Amir Masoud Gharehbaghi; Masahiro Fujita (IEICE Trans. Inf. Syst., 2014)

Trace signal selection methods for post silicon debugging. - Shridhar Choudhary; Amir Masoud Gharehbaghi; Takeshi Matsumoto; Masahiro Fujita (VLSI-SoC, 2015)

Efficient signature-based sub-circuit matching. - Amir Masoud Gharehbaghi; Masahiro Fujita (VLSI-SoC, 2015)

A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality. - Amir Masoud Gharehbaghi; Masahiro Fujita (ATS, 2016)

Fast and Efficient Signature-Based Sub-Circuit Matching. - Amir Masoud Gharehbaghi; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Post Silicon Debugging of Electrical Bugs Using Trace Buffers. - Kentaro Iwata; Amir Masoud Gharehbaghi; Mehdi Baradaran Tahoori; Masahiro Fujita (ATS, 2017)

A new approach for diagnosing bridging faults in logic designs. - Amir Masoud Gharehbaghi; Masahiro Fujita (ISCAS, 2017)

Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults. - Conrad J. Moore; Peikun Wang; Amir Masoud Gharehbaghi; Masahiro Fujita (ISCAS, 2017)

A low-cost approximate 32-point transform architecture. - Heming Sun; Zhengxue Cheng; Amir Masoud Gharehbaghi; Shinji Kimura; Masahiro Fujita (ISCAS, 2017)

A new approach for selecting inputs of logic functions during debug. - Amir Masoud Gharehbaghi; Masahiro Fujita (ISQED, 2017)

A new approach for constructing logic functions after ECO. - Amir Masoud Gharehbaghi; Masahiro Fujita (VLSI-SoC, 2017)

A New Reconfigurable Architecture with Applications to IoT and Mobile Computing. - Amir Masoud Gharehbaghi; Tomohiro Maruoka; Masahiro Fujita (IFIPIoT@WCC, 2018)

C Description Reconstruction Method from a Revised Netlist for ECO Support. - Yusuke Kimura; Amir Masoud Gharehbaghi; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults. - Peikun Wang; Conrad J. Moore; Amir Masoud Gharehbaghi; Masahiro Fujita (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Signal Selection Methods for Efficient Multi-Target Correction. - Yusuke Kimura; Amir Masoud Gharehbaghi; Masahiro Fujita (ISCAS, 2019)

Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints. - Tomohiro Maruoka; Yukio Miyasaka; Akihiro Goda; Amir Masoud Gharehbaghi; Masahiro Fujita (ISCAS, 2019)

High-Level Engineering Change Through Programmable Datapath and SMT Solvers. - Qinhao Wang; Amir Masoud Gharehbaghi; Takeshi Matsumoto; Masahiro Fujita (ISCAS, 2019)

Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults. - Peikun Wang; Amir Masoud Gharehbaghi; Masahiro Fujita (ISQED, 2019)

Approximate Arithmetic Circuit Design Using a Fast and Scalable Method. - Qi Lu; Amir Masoud Gharehbaghi; Masahiro Fujita (VLSI-SoC, 2019)

An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults. - Peikun Wang; Amir Masoud Gharehbaghi; Masahiro Fujita (VTS, 2019)

Signal Selection Methods for Debugging Gate-Level Sequential Circuits. - Yusuke Kimura; Amir Masoud Gharehbaghi; Masahiro Fujita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme. - Heming Sun; Zhengxue Cheng; Amir Masoud Gharehbaghi; Shinji Kimura; Masahiro Fujita (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations. - Masahiro Fujita; Yusuke Kimura; Xingming Le; Yukio Miyasaka; Amir Masoud Gharehbaghi (DATE, 2020)

Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints. - Akihiro Goda; Yukio Miyasaka; Amir Masoud Gharehbaghi; Masahiro Fujita (ISQED, 2020)

A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality. - Peikun Wang; Amir Masoud Gharehbaghi; Masahiro Fujita (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns. - Peikun Wang; Amir Masoud Gharehbaghi; Masahiro Fujita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)