A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. - Prashant Dubey; Gaurav Ahuja; Vaibhav Verma; Sanjay Kumar Yadav; Amit Khanuja (VLSID, 2014)

Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs. - M. Sultan M. Siddiqui; Shailendra Sharad; Yogendra Sharma; Amit Khanuja (VLSID, 2015)

A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision. - Prashant Dubey; Kritika Aditya; Ankur Srivastava; Amit Khanuja; Jamil Kawa; Thu Nguyen (ISCAS, 2017)

Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler. - Vinay Kumar; Neeraj Kapoor; Sudhir Kumar 002; Monila Juneja; Amit Khanuja (VLSID, 2019)