An ECO Technique for Removing Crosstalk Violations in Clock Networks. - Amit Kumar 004; Krishnendu Chakrabarty; Chunduri Rama Mohan (VLSI Design, 2007)

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. - Amit Kumar 004; Sudhakar M. Reddy; Irith Pomeranz; Bernd Becker 001 (DATE, 2011)

Performance aware partitioning for 3D-SOCs. - Amit Kumar 004; Sudhakar M. Reddy; Bernd Becker 001; Irith Pomeranz (ISOCC, 2012)

TSV and DFT cost aware circuit partitioning for 3D-SOCs. - Amit Kumar 004; Sudhakar M. Reddy; Irith Pomeranz; Bernd Becker 001 (ISQED, 2012)

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. - Amit Kumar 004; Janusz Rajski; Sudhakar M. Reddy; Thomas Rinderknecht (Asian Test Symposium, 2013)

On the generation of compact test sets. - Amit Kumar 004; Janusz Rajski; Sudhakar M. Reddy; Chen Wang 014 (ITC, 2013)

Isometric test compression with low toggling activity. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (ITC, 2014)

Isometric Test Data Compression. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)