FPGA Prototype of Low Latency BBS PRNG. - Amit Kumar Panda; Kailash Chandra Ray (iNIS, 2015)

Area-Efficient Parallel-Prefix Binary Comparator. - Amit Kumar Panda; Rakesh Palisetty; Kailash Chandra Ray (iSES, 2019)

Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation. - Amit Kumar Panda; Kailash Chandra Ray (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder. - Amit Kumar Panda; Rakesh Palisetty; Kailash Chandra Ray (IEEE Trans. Circuits Syst., 2020)

A Coupled Variable Input LCG Method and its VLSI Architecture for Pseudorandom Bit Generation. - Amit Kumar Panda; Kailash Chandra Ray (IEEE Trans. Instrum. Meas., 2020)

ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah. - Rakesh Palisetty; Amit Kumar Panda; Kailash Chandra Ray (IEEE Trans. Instrum. Meas., 2021)

A Lightweight Deep Convolutional Neural Network Implemented on FPGA and Android Devices for Detection of Breast Cancer Using Ultrasound Images. - Aditya Vinod; Prabhav Guddati; Amit Kumar Panda; Rajesh Kumar Tripathy (IEEE Access, 2024)