Measurement and modeling of MOS transistor current mismatch in analog IC's. - Eric Felt; Amit Narayan; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1994)

Integrating Data Distribution and Loop Transformations. - J. Ramanujam; Amit Narayan (PP, 1995)

Engineering Change in a Non-Deterministic FSM Setting. - Sunil P. Khatri; Amit Narayan; Sriram C. Krishnan; Kenneth L. McMillan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1996)

Decomposition Techniques for Efficient ROBDD Construction. - Jawahar Jain; Amit Narayan; C. Coelho 001; Sunil P. Khatri; Alberto L. Sangiovanni-Vincentelli; Robert K. Brayton; Masahiro Fujita (FMCAD, 1996)

Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. - Amit Narayan; Jawahar Jain; Masahiro Fujita; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1996)

A study of composition schemes for mixed apply/compose based construction of ROBDDs. - Amit Narayan; Sunil P. Khatri; Jawahar Jain; Masahiro Fujita; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1996)

Logic synthesis for large pass transistor circuits. - Premal Buch; Amit Narayan; A. Richard Newton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

Reachability analysis using partitioned-ROBDDs. - Amit Narayan; Adrian J. Isles; Jawahar Jain; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

A Survey of Techniques for Formal Verification of Combinational Circuits. - Jawahar Jain; Amit Narayan; Masahiro Fujita; Alberto L. Sangiovanni-Vincentelli (ICCD, 1997)

Formal Verification of Combinational Circuit. - Jawahar Jain; Amit Narayan; Masahiro Fujita; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1997)

Wireplanning in logic synthesis. - Wilsin Gosti; Amit Narayan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1998)

Reducing Memory Requirements of Nested Loops for Embedded Systems. - J. Ramanujam; Jinpyo Hong; Mahmut T. Kandemir; Amit Narayan (DAC, 2001)

Improved Symbolic Verification Using Partitioning Techniques. - Subramanian K. Iyer; Debashis Sahoo; Christian Stangier; Amit Narayan; Jawahar Jain (CHARME, 2003)

A Partitioning Methodology for BDD-Based Verification. - Debashis Sahoo; Subramanian K. Iyer; Jawahar Jain; Christian Stangier; Amit Narayan; David L. Dill; E. Allen Emerson (FMCAD, 2004)

Continuation method in multitone harmonic balance. - Suihua Lu; Amit Narayan; Amit Mehrotra (ISCAS (5), 2004)

Analysis techniques for obtaining the steady-state solution of MOS LC oscillators. - Makram M. Mansour; Amit Mehrotra; William W. Walker; Amit Narayan (ISCAS (5), 2004)

Steady-state analysis of voltage and current controlled oscillators. - Amit Mehrotra; Suihua Lu; David C. Lee; Amit Narayan (ICCAD, 2005)

Estimating and reducing the memory requirements of signal processing codes for embedded systems. - J. Ramanujam; Jinpyo Hong; Mahmut T. Kandemir; Amit Narayan; Ankush Agarwal (IEEE Trans. Signal Process., 2006)

GridSpice: A Distributed Simulation Platform for the Smart Grid. - Kyle Anderson; Jimmy Du; Amit Narayan; Abbas El Gamal (IEEE Trans. Ind. Informatics, 2014)