A clock-gating based capture power droop reduction methodology for at-speed scan testing. - Bo Yang; Amit Sanghani; Shantanu Sarangi; Chunsheng Liu (DATE, 2011)

Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. - Amit Sanghani; Bo Yang; Karthikeyan Natarajan; Chunsheng Liu (VTS, 2011)

Test method and scheme for low-power validation in modern SOC integrated circuits. - Bonita Bhaskaran; Amit Sanghani; Kaushik Narayanun; Ayub Abdollahian; Amit Laknaur (VTS, 2016)

Flexible scan interface architecture for complex SoCs. - Milind Sonawane; Sailendra Chadalavada; Shantanu Sarangi; Amit Sanghani; Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Jonathon E. Colburn (VTS, 2016)

Dynamic docking architecture for concurrent testing and peak power reduction. - Milind Sonawane; Pavan Kumar Datla Jagannadha; Sailendra Chadalavada; Shantanu Sarangi; Mahmut Yilmaz; Amit Sanghani; Karthikeyan Natarajan; Jonathon E. Colburn; Anubhav Sinha (VTS, 2016)

A programmable method for low-power scan shift in SoC integrated circuits. - Ran Wang 002; Bonita Bhaskaran; Karthikeyan Natarajan; Ayub Abdollahian; Kaushik Narayanun; Krishnendu Chakrabarty; Amit Sanghani (VTS, 2016)