Circuit clustering using graph coloring. - Amit Singh 001; Malgorzata Marek-Sadowska (ISPD, 1999)

A novel high throughput reconfigurable FPGA architecture. - Amit Singh 001; Luca Macchiarulo; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (FPGA, 2000)

Latency and Latch Count Minimization in Wave Steered Circuits. - Amit Singh 001; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (DAC, 2001)

A Global Routing Technique for Wave-Steering Design Methodology. - Nobuo Funabiki; Amit Singh 001; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (DSD, 2001)

Interconnect pipelining in a throughput-intensive FPGA architecture. - Amit Singh 001; Arindam Mukherjee 001; Malgorzata Marek-Sadowska (FPGA, 2001)

Interconnect Resource-Aware Placement for Hierarchical FPGAs. - Amit Singh 001; Ganapathy Parthasarathy; Malgorzata Marek-Sadowska (ICCAD, 2001)

Interconnect complexity-aware FPGA placement using Rent's rule. - Ganapathy Parthasarathy; Malgorzata Marek-Sadowska; Arindam Mukherjee 001; Amit Singh 001 (SLIP, 2001)

Efficient circuit clustering for area and power reduction in FPGAs. - Amit Singh 001; Malgorzata Marek-Sadowska (FPGA, 2002)

FPGA interconnect planning. - Amit Singh 001; Malgorzata Marek-Sadowska (SLIP, 2002)

Efficient circuit clustering for area and power reduction in FPGAs. - Amit Singh 001; Ganapathy Parthasarathy; Malgorzata Marek-Sadowska (ACM Trans. Design Autom. Electr. Syst., 2002)

PITIA: an FPGA for throughput-intensive applications. - Amit Singh 001; Arindam Mukherjee 001; Luca Macchiarulo; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2003)