An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio. - Amrita Saha; Amitabha Sinha (ICETC, 2009)

A reconfigurable Digital Signal Processor using residue number system. - Sharbari Banerjee; Amitabha Sinha (ISSPA, 2010)

A novel architecture for conversion of binary to single digit double base numbers. - Manideepa Mukherjee; Amitabha Sinha (SIGARCH Comput. Archit. News, 2010)

Conversion of binary to single-term triple base numbers for DSP applications. - Anindita Chakraborty; Amitabha Sinha (SIGARCH Comput. Archit. News, 2011)

High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA). - Malay Das; Amitabha Sinha; Nishant Kumar Giri (SIGARCH Comput. Archit. News, 2011)

A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique. - Satrughna Singha; Aniruddha Ghosh; Amitabha Sinha (SIGARCH Comput. Archit. News, 2011)

A Scheme for Improving Bit Efficiency for Residue Number System. - Chaitali Biswas Dutta; Partha Garai; Amitabha Sinha (ACITY (3), 2012)

Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System - Chaitali Biswas Dutta; Partha Garai; Amitabha Sinha (CoRR, 2012)

A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system. - Aniruddha Ghosh; Satrughna Singha; Amitabha Sinha (SIGARCH Comput. Archit. News, 2012)

"Floating point RNS": a new concept for designing the MAC unit of digital signal processor. - Aniruddha Ghosh; Satrughna Singha; Amitabha Sinha (SIGARCH Comput. Archit. News, 2012)

FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT. - Nishant Kumar Giri; Amitabha Sinha (SIGARCH Comput. Archit. News, 2012)

A new algorithm for computing triple-base number system. - Subhashis Maitra; Amitabha Sinha (SIGARCH Comput. Archit. News, 2012)

Field Programmable DSP Arrays - A - Amitabha Sinha; Soumojit Acharyya; Suranjan Chakraborty; Mitrava Sarkar (CoRR, 2013)

High performance MAC unit for DSP and cryptographic applications. - Subhashis Maitra; Amitabha Sinha (SIGARCH Comput. Archit. News, 2013)

High efficiency MAC unit used in digital signal processing and elliptic curve cryptography. - Subhashis Maitra; Amitabha Sinha (SIGARCH Comput. Archit. News, 2013)

Design and simulation of MAC unit using combinational circuit and adder. - Subhashis Maitra; Amitabha Sinha (SIGARCH Comput. Archit. News, 2013)

FPGA implementation of a novel DCT architecture reducing constant cosine terms. - Santanu Pal; Amitabha Sinha; Pijush Biswas (SIGARCH Comput. Archit. News, 2013)

An integrated development platform of a reconfigurable radio processor for software defined radio. - Amrita Saha; Pijush Biswas; Amitabha Sinha (SIGARCH Comput. Archit. News, 2013)

Performance analysis of a FPGA based novel binary and DBNS multiplier. - Amrita Saha; Manideepa Mukherjee; Debanjana Datta; Sangita Saha; Amitabha Sinha (SIGARCH Comput. Archit. News, 2013)

A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. - Amitabha Sinha; Mitrava Sarkar; Soumojit Acharyya; Suranjan Chakraborty (SIGARCH Comput. Archit. News, 2013)

A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. - Atin Mukherjee 002; Amitabha Sinha; Debesh Choudhury (SIGARCH Comput. Archit. News, 2014)

Trans_Proc: A Reconfigurable Processor to Implement The Linear Transformations. - Atri Sanyal; Amitabha Sinha (Int. J. Softw. Innov., 2022)