Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor. - Melvin A. Breuer; Amitava Majumdar 002; Cauligi S. Raghavendra (ICCD, 1988)

Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. - Amitava Majumdar 002; Cauligi S. Raghavendra; Melvin A. Breuer (IEEE Trans. Computers, 1990)

A Branching Process Model for Observability Analysis of Combinational Circuits. - Sarma Sastry; Amitava Majumdar 002 (DAC, 1991)

Test efficiency analysis of random self-test of sequential circuits. - Sarma Sastry; Amitava Majumdar 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits. - Amitava Majumdar 002; Sarma Sastry (DAC, 1992)

Statistical Analysis of Controllability. - Amitava Majumdar 002; Sarma Sastry (VLSI Design, 1993)

Probabilistic characterization of controllability in general homogeneous circuits. - Amitava Majumdar 002; Sarma Sastry (Comput. Aided Des., 1993)

Deterministic Test Pattern Reproduction by a Counter. - Dimitrios Kagaris; Spyros Tragoudas; Amitava Majumdar 002 (ED&TC, 1996)

On the Use of Counters for Reproducing Deterministic Test Sets. - Dimitrios Kagaris; Spyros Tragoudas; Amitava Majumdar 002 (IEEE Trans. Computers, 1996)

On-Chip Test Embedding for Multi-Weighted Random LFSRs. - Dimitrios Kagaris; Spyros Tragoudas; Amitava Majumdar 002 (DFT, 1998)

Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan. - Amitava Majumdar 002; Michio Komoda; Tim Ayres (VTS, 1998)

Test-set partitioning for multi-weighted random LFSRs. - Dimitri Kagaris; Spyros Tragoudas; Amitava Majumdar 002 (Integr., 2000)

Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. - Kamran Zarrineh; Thomas A. Ziaja; Amitava Majumdar 002 (ICCD, 2001)

A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. - Ishwar Parulkar; Thomas A. Ziaja; Rajesh Pendurkar; Anand D'Souza; Amitava Majumdar 002 (ITC, 2002)

Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. - Olivier Caty; Ismet Bayraktaroglu; Amitava Majumdar 002; Richard Lee; John Bell; Lisa Curhan (ITC, 2003)

Hold time validation on silicon and the relevance of hazards in timing analysis. - Amitava Majumdar 002; Wei-Yu Chen; Jun Guo (DAC, 2006)

Panel: Analog Characterization and Test: The Long Road to Realization. - Arani Sinha; Amitava Majumdar 002; Vasu Ganti (VTS, 2009)

A Novel mechanism for speed characterization during delay test. - Amitava Majumdar 002; Arani Sinha; Nehal Patel; Ramamurthy Setty; Yan Dong; Shu-Hsuan Chou (VTS, 2011)

Special session 5B: Panel How much toggle activity should we be testing with? - Xiaoqing Wen; Mohammad Tehranipoor; Rohit Kapur; Anand Bhat; Amitava Majumdar 002; LeRoy Winemberg (VTS, 2011)

Power Characterization of Embedded SRAMs for Power Binning. - Yang Zhao; Lisa Grenier; Amitava Majumdar 002 (VTS, 2012)

Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies. - Richard Swanson; Anna Wong; Suraj Ethirajan; Amitava Majumdar 002 (ETS, 2014)

Innovative practices session 3C: Solving today's test challenges. - John Kim; Wolfgang Meyer; T. M. Mak; Amitava Majumdar 002 (VTS, 2014)

Innovative practices session 4C: Disruptive solutions in the non-digital world. - Amitava Majumdar 002; Suriya Natarajan; Stephen K. Sunter; Prashant Goteti; Ke Huang 001 (VTS, 2014)

Hot topic session 9C: Test and fault tolerance for emerging memory technologies. - Suriya Natarajan; Amitava Majumdar 002; Jeyavijayan Rajendran (VTS, 2014)

Application debug in FPGAs in the presence of multiple asynchronous clocks. - Georgios Tzimpragos; Da Cheng; Stephanie Tapp; Balakrishna Jayadev; Amitava Majumdar 002 (FPT, 2016)

Special panel session IIB: "System validation and silicon debug - Is standardization possible?". - Mike Ricchetti; Eric Rentschler; Amit Majumdar 002; Mike Lowe; Mark LaVine; Skip Lindsey; Sharad Kumar (VTS, 2016)

Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs. - Amitava Majumdar 002; Balakrishna Jayadev; Da Cheng; Albert Lin (ATS, 2017)

Field profiling & monitoring of payload transistors in FPGAs. - Da Cheng; Amitava Majumdar 002; Xiaobao Wang; Nui Chong (IOLTS, 2017)

A digital clock-less pulse stretcher with application in deep sub-nanosecond pulse detection. - Zhiqiang Liu; Nanqi Liu; Shravan K. Chaganti; Degang Chen 001; Amitava Majumdar 002 (ISCAS, 2017)

Foreword. - Yiorgos Makris; Srivaths Ravi 001; Amit Majumdar 002 (VTS, 2017)

Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features. - Amitava Majumdar 002; Balakrishna Jayadev (ATS, 2018)

Concurrent Sampling with Local Digitization - An Alternative to Analog Test Bus. - Nanqi Liu; Shravan K. Chaganti; Zhiqiang Liu; Degang Chen 001; Amitava Majumdar 002 (ISCAS, 2018)

Innovative Design for Test in State-of-the-Art Analog Systems. - Hans Martin von Staudt; Amit Majumdar 002; Bill Taylor; Jennifer Kitchen (VTS, 2019)