Verification of decimal floating-point fused-multiply-add operation. - Amr A. R. Sayed-Ahmed; Hossam A. H. Fahmy; Rodina Samy (AICCSA, 2011)

Verification of the decimal floating-point square root operation. - Amr A. R. Sayed-Ahmed; Hossam A. H. Fahmy; Ulrich Kühne (ETS, 2014)

Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. - Amr A. R. Sayed-Ahmed; Ulrich Kühne; Daniel Große; Rolf Drechsler (ISVLSI, 2015)

Formal verification of integer multipliers by combining Gröbner basis with logic reduction. - Amr A. R. Sayed-Ahmed; Daniel Große; Ulrich Kühne; Mathias Soeken; Rolf Drechsler (DATE, 2016)

Equivalence checking using Gröbner bases. - Amr A. R. Sayed-Ahmed; Daniel Große; Mathias Soeken; Rolf Drechsler (FMCAD, 2016)

Highly Automated Formal Verification of Arithmetic Circuits. - Amr A. R. Sayed-Ahmed (2017)