2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing. - Amr Elshazly; Khaled M. Sharaf (ISCAS, 2006)

A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. - Brian Young; Sunwoo Kwon; Amr Elshazly; Pavan Kumar Hanumolu (CICC, 2010)

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. - Amr Elshazly; Rajesh Inti; Wenjing Yin; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2011)

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. - Rajesh Inti; Amr Elshazly; Brian Young; Wenjing Yin; Marcel A. Kossel; Thomas Toifl; Pavan Kumar Hanumolu (ISSCC, 2011)

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. - Rajesh Inti; Wenjing Yin; Amr Elshazly; Naga Sasidhar; Pavan Kumar Hanumolu (ISSCC, 2011)

A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. - Wenjing Yin; Rajesh Inti; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2011)

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. - Amr Elshazly; Rajesh Inti; Wenjing Yin; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2011)

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. - Rajesh Inti; Wenjing Yin; Amr Elshazly; Naga Sasidhar; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2011)

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. - Wenjing Yin; Rajesh Inti; Amr Elshazly; Mrunmay Talegaonkar; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2011)

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. - Wenjing Yin; Rajesh Inti; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2011)

A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. - Amr Elshazly; Rajesh Inti; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2012)

A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. - Amr Elshazly; Sachin Rao; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2012)

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. - Karthikeyan Reddy; Sachin Rao; Rajesh Inti; Brian Young; Amr Elshazly; Mrunmay Talegaonkar; Pavan Kumar Hanumolu (ISSCC, 2012)

A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. - Amr Elshazly; Rajesh Inti; Mrunmay Talegaonkar; Pavan Kumar Hanumolu (VLSIC, 2012)

A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control. - Qadeer Khan; Amr Elshazly; Sachin Rao; Rajesh Inti; Pavan Kumar Hanumolu (VLSIC, 2012)

A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. - Karthikeyan Reddy; Sachin Rao; Rajesh Inti; Brian Young; Amr Elshazly; Mrunmay Talegaonkar; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2012)

A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. - Tejasvi Anand; Mrunmay Talegaonkar; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2013)

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. - Amr Elshazly; Rajesh Inti; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2013)

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. - Ahmed Elkholy; Amr Elshazly; Saurabh Saxena; Guanghua Shu; Pavan Kumar Hanumolu (ISSCC, 2014)

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Tejasvi Anand; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2014)

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. - Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. - Amr Elshazly; Ajay Balankutty; Yan-Yu Huang; Kai Yu 016; Frank O'Mahony (VLSIC, 2014)

A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW. - Qadeer Ahmad Khan; Seong Joong Kim; Mrunmay Talegaonkar; Amr Elshazly; Arun Rao; Nathanael Griesert; Greg Winter; William McIntyre; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (VLSIC, 2014)

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2014)

A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators. - Brian Young; Karthik Reddy; Sachin Rao; Amr Elshazly; Tejasvi Anand; Pavan Kumar Hanumolu (VLSIC, 2014)

A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. - Tejasvi Anand; Amr Elshazly; Mrunmay Talegaonkar; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques. - Amr Elshazly; Sachin Rao; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. - Guanghua Shu; Saurabh Saxena; Woo-Seok Choi; Mrunmay Talegaonkar; Rajesh Inti; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. - Mrunmay Talegaonkar; Amr Elshazly; Karthikeyan Reddy; Praveen Prabha; Tejasvi Anand; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. - Ahmed Elkholy; Saurabh Saxena; Romesh Kumar Nandwana; Amr Elshazly; Pavan Kumar Hanumolu (CICC, 2015)

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. - Tejasvi Anand; Mrunmay Talegaonkar; Ahmed Elkholy; Saurabh Saxena; Amr Elshazly; Pavan Kumar Hanumolu (ISSCC, 2015)

3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. - Jihwan Kim; Ajay Balankutty; Amr Elshazly; Yan-Yu Huang; Hang Song; Kai Yu 016; Frank O'Mahony (ISSCC, 2015)

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. - Tejasvi Anand; Mrunmay Talegaonkar; Ahmed Elkholy; Saurabh Saxena; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. - Woo-Seok Choi; Tejasvi Anand; Guanghua Shu; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. - Ahmed Elkholy; Tejasvi Anand; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

High Frequency Buck Converter Design Using Time-Based Control Techniques. - Seong Joong Kim; Qadeer Khan; Mrunmay Talegaonkar; Amr Elshazly; Arun Rao; Nathanael Griesert; Greg Winter; William McIntyre; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. - Romesh Kumar Nandwana; Tejasvi Anand; Saurabh Saxena; Seong Joong Kim; Mrunmay Talegaonkar; Ahmed Elkholy; Woo-Seok Choi; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2015)

19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. - Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Amr Elshazly; Nasser A. Kurd (ISSCC, 2016)

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. - Ahmed Elkholy; Saurabh Saxena; Romesh Kumar Nandwana; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. - Guanghua Shu; Woo-Seok Choi; Saurabh Saxena; Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2016)

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. - Romesh Kumar Nandwana; Saurabh Saxena; Amr Elshazly; Kartikeya Mayaram; Pavan Kumar Hanumolu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. - Jihwan Kim; Ajay Balankutty; Rajeev K. Dokania; Amr Elshazly; Hyung Seok Kim; Sandipan Kundu; Skyler Weaver; Kai Yu 016; Frank O'Mahony (ISSCC, 2018)

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. - Ahmed Elkholy; Saurabh Saxena; Guanghua Shu; Amr Elshazly; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2018)

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. - Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Mark Neidengard; Nasser A. Kurd; Amr Elshazly (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. - Jihwan Kim; Ajay Balankutty; Rajeev K. Dokania; Amr Elshazly; Hyung Seok Kim; Sandipan Kundu; Dan Shi; Skyler Weaver; Kai Yu 016; Frank O'Mahony (IEEE J. Solid State Circuits, 2019)