A novel power gated digitally controlled oscillator. - Amr M. Lotfy; Maged Ghoneima; Mohamed Abdel-Moneum (ICEAC, 2011)

Modeling the response of Bang-Bang digital PLLs to phase error perturbations. - Moataz Abdelfattah; Maged Ghoneima; Yehea I. Ismail; Amr Lotfy; Mohamed Abdel-moneum; Nasser A. Kurd; Greg Taylor (CICC, 2012)

A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. - Sally Safwat; Amr Lotfy; Maged Ghoneima; Yehea I. Ismail (ISCAS, 2012)

A novel digital loop filter architecture for bang-bang ADPLL. - Moataz Abdelfattah; Maged Ghoneima; Yehea I. Ismail; Amr Lotfy; Mohamed Abdelsalam; Mohamed Abdel-moneum; Nasser A. Kurd; Greg Taylor (SoCC, 2012)

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. - Amr Lotfy; Syed Feruz Syed Farooq; Qi S. Wang; Soner Yaldiz; Praveen Mosalikanti; Nasser A. Kurd (CICC, 2015)

A fast locking hybrid TDC-BB ADPLL utilizing proportional derivative digital loop filter and power gated DCO. - Amr Lotfy; Maged Ghoneima; Mohamed Abdel-Moneum (ISCAS, 2016)