Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. - Amr M. S. Tosson; Siddharth Garg; Mohab H. Anis (VLSI-SoC, 2013)

8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design. - Amr M. S. Tosson Abdelwahed; Adam Neale; Mohab H. Anis; Lan Wei (ACM Great Lakes Symposium on VLSI, 2016)

RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO2/Hf 1T1R RRAM Memory Cell. - Amr M. S. Tosson; Mohab H. Anis; Lan Wei (ACM Great Lakes Symposium on VLSI, 2016)

1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. - Amr M. S. Tosson; Shimeng Yu; Mohab H. Anis; Lan Wei (ASICON, 2017)

Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems. - Amr M. S. Tosson; Shimeng Yu; Mohab H. Anis; Lan Wei (ACM Great Lakes Symposium on VLSI, 2017)

Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems. - Amr M. S. Tosson; Shimeng Yu; Mohab H. Anis; Lan Wei (ISVLSI, 2017)

A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems. - Amr M. S. Tosson; Shimeng Yu; Mohab H. Anis; Lan Wei (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Novel Programmable Variation-Tolerant RRAM-based Delay Element Circuit. - Kangqiang Pan; Amr M. S. Tosson; Norman Y. Zhou; Lan Wei (NANOARCH, 2021)

Error Resilience and Recovery of Process Induced Stuck-at Faults in MLP Neural Networks using Emerging Technology. - An Qi Zhang; Amr M. S. Tosson; Lan Wei (NANOARCH, 2021)

A Novel 2T2R CR-based TCAM Design for High-speed and Energy-efficient Applications. - Kangqiang Pan; Amr M. S. Tosson; Ningxuan Wang; Norman Y. Zhou; Lan Wei (ACM Great Lakes Symposium on VLSI, 2022)