Fully integrated low phase-noise PLLs using closed-loop voltage-to-frequency converter architectures. - Amr N. Hafez; Mohamed I. Elmasry (CICC, 1999)

A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers. - Amr N. Hafez; Mohamed I. Elmasry (Great Lakes Symposium on VLSI, 1999)

A low power monolithic subsampled phase-locked loop architecture for wireless transceivers. - Amr N. Hafez; Mohamed I. Elmasry (ISCAS (2), 1999)

A fully-integrated low phase-noise nested-loop PLL for frequency synthesis. - Amr N. Hafez; Mohamed I. Elmasry (CICC, 2000)

A 2.7 GHz super-regenerative receiver front-end for QPSK modulated signals. - Ghada H. Ibrahim; Amr N. Hafez; Ahmed Hussien Khalil; H. A. Elsimary (CSNDSP, 2012)

A simple digital detection scheme for demodulating QPSK signals in super-regenerative receiver architecture. - Ghada H. Ibrahim; Amr N. Hafez; Ahmed Hussien Khalil (IDT, 2013)

An 8-PSK digital phase detection technique for super-regenerative receivers. - Ghada H. Ibrahim; Amr N. Hafez (ICECS, 2015)