A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter. - D. Meganathan; S. Moorthi; Amrith Sukumaran; M. M. Dinesh Babu; J. Raja Paul Perinbam (J. Low Power Electron., 2008)

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC. - D. Meganathan; Amrith Sukumaran; M. M. Dinesh Babu; S. Moorthi; R. Deepalakshmi (Microelectron. J., 2009)

Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback. - Amrith Sukumaran; Shanthi Pavan (IEEE J. Solid State Circuits, 2014)

A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC. - Amrith Sukumaran; Shanthi Pavan (ESSCIRC, 2015)

15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts. - Sujith Billa; Amrith Sukumaran; Shanthi Pavan (ISSCC, 2016)

Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs. - Amrith Sukumaran; Shanthi Pavan (IEEE J. Solid State Circuits, 2016)

Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping. - Sujith Billa; Amrith Sukumaran; Shanthi Pavan (IEEE J. Solid State Circuits, 2017)

Multi-Electroanalytical Method Capable, Duty-Cycled, 0.36 mm2 Electrochemical Frontend, Achieving 170dB Current Sensing Range with Extended Compliance Voltage Adopting Feedforward Cancellation. - Amrith Sukumaran; Francesco Caruso; Régis Cattenoz; B. Putter; Jean-Luc Nagel; R. Ravanilla; I. Stergiou; G. Bouilly; P. Nussbaum; Stéphane Emery (CICC, 2025)

A high-PSRR and low-noise CMOS-based reference with barrel shifting and notch filtering. - Amrith Sukumaran; Enrico Miotello; Chun-Min Zhang; Francesco Caruso; Paula Blanca Cruz; Stéphane Emery (ISCAS, 2025)