19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC. - Fazil Ahmad; Greg Unruh; Amrutha Iyer; Pin-En Su; Sherif Abdalla; Bo Shen; Mark Chambers; Ichiro Fujimori (ISSCC, 2016)

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling. - Fazil Ahmad; Greg Unruh; Amrutha Iyer; Pin-En Su; Sherif Abdalla; Bo Shen; Mark Chambers; Ichiro Fujimori (IEEE J. Solid State Circuits, 2017)

A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers. - Arik Zafrany; Daniel Burgos; Li Cai; Sau Siong Chong; Colin Cramm; Sadegh Dadash; Vishal Giridharan; Vivek Gurumoorthy; Belal Helal; Cheng-Ru Ho; Amrutha Iyer; Steve Jantzi; et al. (OFC, 2023)

7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET. - J. Q. Wang; Amber Tan; Amrutha Iyer; A. Fan; A. Farhoodfar; B. Alnabulsi; B. Smith; Chang-Feng Loi; Cheng-Ru Ho; D. Cartina; Jamal Riani; J. Casanova; et al. (ISSCC, 2024)

A 212Gb/s PAM-4 Retimer with Integrated High-Swing Optical Driver and Chip-to-Module Long Reach Capability of 40dB in 5nm FinFET. - V. Gurumoorthy; A. Tan; Amrutha Iyer; A. Fan; A. Farhoodfar; B. Alnabulsi; Belal Helal; Cindra Abidin; C. Loi; D. Cartina; H. Lo; Ivan Fabiano; et al. (ISSCC, 2025)