A formal method to improve SystemVerilog functional coverage. - An-Che Cheng; Chia-Chih Yen; Jing-Yang Jou (HLDVT, 2012)

Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. - An-Che Cheng; Chia-Chih Jack Yen; Celina G. Val; Sam Bayless; Alan J. Hu; Iris Hui-Ru Jiang; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2014)

Resource-aware functional ECO patch generation. - An-Che Cheng; Iris Hui-Ru Jiang; Jing-Yang Jou (DATE, 2016)