Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study. - Ben Kaczer; Robin Degraeve; Mahmoud Rasras; An De Keersgieter; K. Van de Mieroop; Guido Groeseneken (Microelectron. Reliab., 2002)

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? - Thomas Chiarella; Liesbeth Witters; Abdelkarim Mercha; Christoph Kerner; Rok Dittrich; Michal Rakowski; Claude Ortolland; Lars-Åke Ragnarsson; Bertrand Parvais; An De Keersgieter; Stefan Kubicek; Augusto Redolfi; et al. (ESSCIRC, 2009)

STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. - Doyoung Jang; Marie Garcia Bardon; Dmitry Yakimets; Kenichi Miyaguchi; An De Keersgieter; Thomas Chiarella; Romain Ritzenthaler; Morin Dehan; Abdelkarim Mercha (ESSDERC, 2013)

FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. - Geert Eneman; An De Keersgieter; Anda Mocuta; Nadine Collaert; Aaron Thean (ICICDT, 2015)

Origins and implications of increased channel hot carrier variability in nFinFETs. - Ben Kaczer; Jacopo Franco; M. Cho; Tibor Grasser; Philippe J. Roussel; Stanislav Tyaginov; M. Bina; Yannick Wimmer; Luis-Miguel Procel; Lionel Trojman; Felice Crupi; Gregory Pitner; et al. (IRPS, 2015)

Towards high performance sub-10nm finW bulk FinFET technology. - Thomas Chiarella; Stefan Kubicek; E. Rosseel; Romain Ritzenthaler; Andriy Hikavyy; P. Eyben; An De Keersgieter; L.-Å. Ragnarsson; M.-S. Kim; S.-A. Chew; Tom Schram; S. Demuynck; et al. (ESSDERC, 2016)

Isolation of nanowires made on bulk wafers by ground plane doping. - Romain Ritzenthaler; Hans Mertens; An De Keersgieter; Jérôme Mitard; Dan Mocuta; N. Horiguchi (ESSDERC, 2017)

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. - Anabela Veloso; Geert Eneman; An De Keersgieter; P. Favia; Andriy Hikavyy; Rongmei Chen; Anne Jourdain; N. Horiguchi (ICICDT, 2022)

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors. - Stanislav Tyaginov; Alexander Makarov; Al-Moatasem Bellah El-Sayed; Adrian Vaisman Chasin; Erik Bury; Markus Jech; Michiel Vandemaele; Alexander Grill; An De Keersgieter; Mikhail I. Vexler; Geert Eneman; Ben Kaczer (IRPS, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)