Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. - Tianzhu Xiong; Yongliang Zhou; Yuyao Kong; Bo Wang 023; An Guo 001; Yufei Wang; Chen Xue; Haiming Hsu; Xin Si; Jun Yang 006 (ISOCC, 2021)

A Quantization Model Based on a Floating-point Computing-in-Memory Architecture. - Xi Chen 107; An Guo 001; Xinbing Xu; Xin Si; Jun Yang 006 (APCCAS, 2022)

A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model. - Zhongyuan Feng; Bo Wang 023; Zhaoyang Zhang; An Guo 001; Xin Si (APCCAS, 2022)

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. - An Guo 001; Yongliang Zhou; Bo Wang 023; Tianzhu Xiong; Chen Xue; Yufei Wang; Xin Si; Jun Yang 006 (ISCAS, 2022)

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. - Bo Wang 023; Chen Xue; Han Liu; Xiang Li; Anran Yin; Zhongyuan Feng; Yuyao Kong; Tianzhu Xiong; Haiming Hsu; Yongliang Zhou; An Guo 001; Yufei Wang; et al. (ISCAS, 2022)

VCCIM: a voltage coupling based computing-in-memory architecture in 28 nm for edge AI applications. - An Guo 001; Chen Xue; Xi Chen 107; Xin Si (CCF Trans. High Perform. Comput., 2022)

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. - Bo Wang 023; Chen Xue; Zhongyuan Feng; Zhaoyang Zhang; Han Liu; Lizheng Ren; Xiang Li; Anran Yin; Tianzhu Xiong; Yeyang Xue; Shengnan He; Yuyao Kong; et al. (ISSCC, 2023)

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. - Zhaoyang Zhang; Jinwu Chen; Xi Chen 107; An Guo 001; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xingyu Pu; Shengnan He; Xin Si; Jun Yang 006 (Sci. China Inf. Sci., 2023)

A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. - An Guo 001; Xueshan Dong; Fangyuan Dong; Dongqi Li; Yiran Zhang; Jingmin Zhang; Yuchen Tang; Yuhui Shi; Xiao Tan; Bo Liu 019; Weiwei Shan; Hao Cai 001; et al. (A-SSCC, 2024)

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang; Zhichao Liu; Feiran Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; Yuchen Tang; et al. (CICC, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. - Xi Chen 107; Yitong Zhao; An Guo 001; Jinwu Chen; Fangyuan Dong; Zhaoyang Zhang; Tianzhu Xiong; Bo Wang 023; Yuyao Kong; Xin Si (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Chen Xi; Fangyuan Dong; Xingyu Pu; Dongqi Li; Jingmin Zhang; Xueshan Dong; Hui Gao; Yiran Zhang; Bo Wang 023; Jun Yang 006; Xin Si (IEEE J. Solid State Circuits, 2024)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers. - Xing Wang; Tianhui Jiao; Yi Yang 001; Shaochen Li; Dongqi Li; An Guo 001; Yuhui Shi; Yuchen Tang; Jinwu Chen; Zhican Zhang; Zhichao Liu; Bo Liu 019; et al. (ISSCC, 2025)

A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang; Yanqi Zhang; Feiran Liu; Zhichao Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; et al. (IEEE J. Solid State Circuits, 2025)