A High Throughput-Rate Architecture for 8*8 2-D DCT. - Ming-Hwa Sheu; Jau-Yien Lee; Jhing-Fa Wang; An-Nan Suen; Lian-Ying Liu (ISCAS, 1993)

A Bayesian neural network chip design for speech recognition system. - Jhing-Fa Wang; An-Nan Suen; Jia-Ru Lee; Chung-Hsien Wu 001 (ICNN, 1995)

A Cepstrum Chip: Architecture and Implementation. - An-Nan Suen; Jhing-Fa Wang; Yuen-Lin Chiang (ISCAS, 1995)

A programmable application-specific CELP processor with parallel architectures. - An-Nan Suen; Jhing-Fa Wang; Bor-Yueh Liu (ICASSP, 1996)

VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements. - An-Nan Suen; Jhing-Fa Wang; Jia-Lang Lin (Integr., 1997)

A programmable application-specific VLSI architecture for speech recognition. - Jia-Ching Wang; Jhing-Fa Wang; An-Nan Suen; Yu-Sheng Weng (ICECS, 2001)

VLSI Architecture and Implementation for Speech Recognizer Based on Discriminative Bayesian Neural Network. - Jhing-Fa Wang; Jia-Ching Wang; An-Nan Suen; Chung-Hsien Wu 001; Fan-Min Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)