Constrained interpolation for guided logic synthesis. - Ana Petkovska; David Novo; Alan Mishchenko; Paolo Ienne (ICCAD, 2014)

Improved carry chain mapping for the VTR flow. - Ana Petkovska; Grace Zgheib; David Novo; Muhsen Owaida; Alan Mishchenko; Paolo Ienne (FPT, 2015)

Fast hierarchical NPN classification. - Ana Petkovska; Mathias Soeken; Giovanni De Micheli; Paolo Ienne; Alan Mishchenko (FPL, 2016)

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. - Ana Petkovska; Alan Mishchenko; Mathias Soeken; Giovanni De Micheli; Robert K. Brayton; Paolo Ienne (ICCAD, 2016)

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. - Mathias Soeken; Alan Mishchenko; Ana Petkovska; Baruch Sterin; Paolo Ienne; Robert K. Brayton; Giovanni De Micheli (SAT, 2016)

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. - Zhufei Chu; Xifan Tang; Mathias Soeken; Ana Petkovska; Grace Zgheib; Luca Gaetano Amarù; Yinshui Xia; Paolo Ienne; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2017)

Exploiting Satisfiability Solvers for Efficient Logic Synthesis. - Ana Petkovska (2017)

Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. - Ana Petkovska; Alan Mishchenko; David Novo; Muhsen Owaida; Paolo Ienne (Advanced Logic Synthesis, 2018)

Canonical computation without canonical representation. - Alan Mishchenko; Robert K. Brayton; Ana Petkovska; Mathias Soeken; Luca G. Amarù; Antun Domic (DAC, 2018)