Design and implementation of an embedded 512KB level 2 cache subsystem. - Jinuk Luke Shin; Bruce Petrick; Howard Levy; Jinseung Son; Mandeep Singh; Vikas Mathur; Jung-Cheng Yeh; Heesung Choi; Vishal Gupta; Tom Ziaja; Ana Sonia Leon (CICC, 2004)

A dual-core 64b ultraSPARC microprocessor for dense server applications. - Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Ana Sonia Leon (DAC, 2004)

Design and implementation of an embedded 512-KB level-2 cache subsystem. - Jinuk Luke Shin; Bruce Petrick; Mandeep Singh; Ana Sonia Leon (IEEE J. Solid State Circuits, 2005)

A dual-core 64-bit ultraSPARC microprocessor for dense server applications. - Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Howard Levy; Ha Pham; Jinseung Son; Nathan Moon; Dina Bistry; Umesh Nair; Mandeep Singh; Vikas Mathur; et al. (IEEE J. Solid State Circuits, 2005)

The UltraSPARC T1 Processor: CMT Reliability. - Ana Sonia Leon; Brian Langley; Jinuk Luke Shin (CICC, 2006)

A Power-Efficient High-Throughput 32-Thread SPARC Processor. - Ana Sonia Leon; Jinuk Luke Shin; Kenway W. Tam; William Bryg; Francis Schumacher; Poonacha Kongetira; David Weisner; Allan Strong (ISSCC, 2006)

A Power-Efficient High-Throughput 32-Thread SPARC Processor. - Ana Sonia Leon; Kenway W. Tam; Jinuk Luke Shin; David Weisner; Francis Schumacher (IEEE J. Solid State Circuits, 2007)

A 40nm 16-core 128-thread CMT SPARC SoC processor. - Jinuk Luke Shin; Kenway W. Tam; Dawei Huang; Bruce Petrick; Ha Pham; Changku Hwang; Hongping Penny Li; Alan P. Smith 002; Timothy Johnson; Francis Schumacher; David Greenhill; Ana Sonia Leon; et al. (ISSCC, 2010)

A 40 nm 16-Core 128-Thread SPARC SoC Processor. - Jinuk Luke Shin; Dawei Huang; Bruce Petrick; Changku Hwang; Kenway W. Tam; Alan P. Smith 002; Ha Pham; Hongping Penny Li; Timothy Johnson; Francis Schumacher; Ana Sonia Leon; Allan Strong (IEEE J. Solid State Circuits, 2011)