VLSI Architecture Design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application. - Anagha Nimbekar; Y. V. Sai Dinesh; Arvind Gautam; Vidhumouli Hunsigida; Appa Rao Nali; Amit Acharyya (LASCAS, 2022)

SqueezeVGGNet: A Methodology for designing low complexity VGG Architecture for Resource Constraint Edge Applications. - Ramesh Reddy Chandrapu; Chandrajit Pal; Anagha Nimbekar; Amit Acharyya (NEWCAS, 2022)

Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference Accelerator. - Anagha Nimbekar; Chandrasekhara Srinivas Vatti; Y. V. Sai Dinesh; Sunidhi Singh; Tarun Gupta; Ramesh Reddy Chandrapu; Amit Acharyya (SOCC, 2022)

Digital Twin Based Fault-Tolerance Framework for RRAM Based Neural Computing Systems. - Chandrasekhara Srinivas Vatti; Y. V. Sai Dinesh; Anagha Nimbekar; Amit Acharyya (MWSCAS, 2023)

Reconfigurable VLSI Design Architecture for Deep Learning Established Forelimb and Hindlimb Gesture Recognition for Rehabilitation Application. - Anagha Nimbekar; Y. V. Sai Dinesh; Arvind Gautam; Vidhumouli Hunsigida; Appa Rao Nali; Amit Acharyya (IEEE Access, 2023)

Bayesian Inference Accelerator for Spiking Neural Networks. - Prabodh Katti; Anagha Nimbekar; Chen Li; Amit Acharyya; Bashir M. Al-Hashimi; Bipin Rajendran (ISCAS, 2024)

Multiple PUF-CPRNG based Authentication Methodology for Protecting the IP Cores. - Agshare Dheeraj; Pabitra Das; Y. V. Sai Dinesh; Anagha Nimbekar; Amit Acharyya (SOCC, 2024)

Hardware-Software Co-optimised Fast and Accurate Deep Reconfigurable Spiking Inference Accelerator Architecture Design Methodology. - Anagha Nimbekar; Prabodh Katti; Chen Li; Bashir M. Al-Hashimi; Amit Acharyya; Bipin Rajendran (SOCC, 2024)