Rethinking NoCs for Spatial Neural Network Accelerators. - Hyoukjun Kwon; Ananda Samajdar; Tushar Krishna (NOCS, 2017)

MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects. - Hyoukjun Kwon; Ananda Samajdar; Tushar Krishna (ASPLOS, 2018)

GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware. - Ananda Samajdar; Parth Mannan; Kartikay Garg; Tushar Krishna (MICRO, 2018)

SCALE-Sim: Systolic CNN Accelerator. - Ananda Samajdar; Yuhao Zhu 001; Paul N. Whatmough; Matthew Mattina; Tushar Krishna (CoRR, 2018)

A Communication-Centric Approach for Designing Flexible DNN Accelerators. - Hyoukjun Kwon; Ananda Samajdar; Tushar Krishna (IEEE Micro, 2018)

Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. - Ananda Samajdar; Tushar Garg; Tushar Krishna; Nachiket Kapre (FPL, 2019)

SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training. - Eric Qin 001; Ananda Samajdar; Hyoukjun Kwon; Vineet Nadella; Sudarshan Srinivasan; Dipankar Das 002; Bharat Kaul; Tushar Krishna (HPCA, 2020)

CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices. - Parth Mannan; Ananda Samajdar; Tushar Krishna (ISPASS, 2020)

A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim. - Ananda Samajdar; Jan Moritz Joseph; Yuhao Zhu 001; Paul N. Whatmough; Matthew Mattina; Tushar Krishna (ISPASS, 2020)

Data Orchestration in Deep Learning Accelerators - Tushar Krishna; Hyoukjun Kwon; Angshuman Parashar; Michael Pellauer; Ananda Samajdar (Morgan & Claypool Publishers, 2020)

RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. - Geonhwa Jeong; Eric Qin 001; Ananda Samajdar; Christopher J. Hughes; Sreenivas Subramoney; Hyesoon Kim; Tushar Krishna (DAC, 2021)

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. - Jan Moritz Joseph; Ananda Samajdar; Lingjun Zhu; Rainer Leupers; Sung Kyu Lim; Thilo Pionteck; Tushar Krishna (ISQED, 2021)

Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration. - Ananda Samajdar; Michael Pellauer; Tushar Krishna (CoRR, 2021)

AIRCHITECT: Learning Custom Architecture Design and Mapping Space. - Ananda Samajdar; Jan Moritz Joseph; Matthew Denton; Tushar Krishna (CoRR, 2021)

Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. - Ananda Samajdar; Eric Qin 001; Michael Pellauer; Tushar Krishna (DAC, 2022)

Methodology and Analysis for Efficient Custom Architecture Design using Machine Learning. - Ananda Samajdar (2022)

AIrchitect: Automating Hardware Architecture and Mapping Optimization. - Ananda Samajdar; Jan Moritz Joseph; Tushar Krishna (DATE, 2023)

Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Ritik Raj; Chaojian Li; Haoran You; Yonggan Fu; Cheng Wan 005; Ananda Samajdar; Yingyan Celine Lin; Tushar Krishna; Arijit Raychowdhury (ISPASS, 2024)

Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Ritik Raj; Chaojian Li; Haoran You; Yonggan Fu; Cheng Wan 005; Sixu Li; Youbin Kim; Ananda Samajdar; Yingyan Celine Lin; et al. (CoRR, 2024)

CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design. - Zishen Wan; Hanchen Yang; Ritik Raj; Che-Kai Liu; Ananda Samajdar; Arijit Raychowdhury; Tushar Krishna (HPCA, 2025)

NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI. - Hanchen Yang; Zishen Wan; Ritik Raj; Joongun Park; Ziwei Li; Ananda Samajdar; Arijit Raychowdhury; Tushar Krishna (CoRR, 2025)