Online cache state dumping for processor debug. - Anant Vishnoi; Preeti Ranjan Panda; M. Balakrishnan (DAC, 2009)

Cache aware compression for processor debug support. - Anant Vishnoi; Preeti Ranjan Panda; M. Balakrishnan (DATE, 2009)

Enhancing post-silicon processor debug with Incremental Cache state Dumping. - Preeti Ranjan Panda; Anant Vishnoi; M. Balakrishnan (VLSI-SoC, 2010)

Compressing Cache State for Postsilicon Processor Debug. - Preeti Ranjan Panda; M. Balakrishnan; Anant Vishnoi (IEEE Trans. Computers, 2011)