A Reduced-sp- ( hbox {D3L}_{ mathrm{sum}} ) Adder-Based High Frequency (4 times 4 ) Bit Multiplier Using Dadda Algorithm. - Zain Shabbir; Anas Razzaq Ghumman; Shabbir Majeed Chaudhry (Circuits Syst. Signal Process., 2016)

A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS. - Anas Razzaq Ghumman; Shabbir Majeed Chaudhry (Circuits Syst. Signal Process., 2018)

LDPC check node implementation using reversible logic. - Muhammad Awais 004; Anas Razzaq; Ashfaq Ahmed; Guido Masera (IET Circuits Devices Syst., 2019)

Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. - Sajjad Rostami Sani; Farheen Fatima Khan; Anas Razzaq; Andy Gean Ye (FPL, 2020)

Static power model for CMOS and FPGA circuits. - Anas Razzaq; Andy Gean Ye (IET Comput. Digit. Tech., 2021)

Designing efficient FPGA tiles for power-constrained ultra-low-power applications. - Anas Razzaq; Sajjad Rostami Sani; Andy Gean Ye (Integr., 2021)

Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm. - Sajjad Rostami Sani; Anas Razzaq; Andy Gean Ye (FCCM, 2022)

The effect of gate voltage boosting on the power efficiency of multi-context FPGAs. - Anas Razzaq; Sajjad Rostami Sani; Andy Gean Ye (Integr., 2022)

Measuring the Minimum Power Requirement of FPGA Architectural Specifications. - Andy Gean Ye; Anas Razzaq (FPGA, 2025)