Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL. - Rosario M. Reas; Anastacia B. Alvarez; Joy Alinda P. Reyes (UKSim, 2010)

A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design. - Jestoni V. Zarsuela; Anastacia B. Alvarez; Joy Alinda Reyes (UKSim, 2010)

Static Noise Margin of 6T SRAM Cell in 90-nm CMOS. - Christiensen D. C. Arandilla; Anastacia B. Alvarez; Christian Raymund K. Roque (UKSim, 2011)

Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. - Wenfeng Zhao; Yajun Ha; Chin Hau Hoo; Anastacia B. Alvarez (ISLPED, 2013)

14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm. - Anastacia B. Alvarez; Wenfeng Zhao; Massimo Alioto (ISSCC, 2015)

A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range. - Wenfeng Zhao; Anastacia B. Alvarez; Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm. - Anastacia B. Alvarez; Wenfeng Zhao; Massimo Alioto (IEEE J. Solid State Circuits, 2016)

EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS. - Anastacia B. Alvarez; Gopalakrishnan Ponnusamy; Massimo Alioto (A-SSCC, 2017)

A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm. - Sachin Taneja; Anastacia B. Alvarez; Gopalakrishnan Sadagopan; Massimo Alioto (A-SSCC, 2017)

Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. - Fredrick Angelo R. Galapon; Mark Allen D. C. Agaton; Arcel G. Leynes; Lemuel Neil M. Noveno; Anastacia B. Alvarez; Chris Vincent J. Densing; John Richard E. Hizon; Marc D. Rosales; Maria Theresa G. de Leon; Rico Jossel M. Maestro (NGCAS, 2018)

A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications. - Uziel Rein Agub; Jhake Zebedee Aquino; Justine Beano; Rommel Monsayac; Anastacia B. Alvarez; Maria Theresa G. de Leon; Chris Vincent J. Densing; John Richard E. Hizon; Rico Jossel M. Maestro; Marc D. Rosales (TENCON, 2018)

Design and Implementation of a Thermoelectric Energy Harvesting Interface Circuit with Maximum Power Point Tracking and Self-Startup Capability for Wireless Sensor Nodes. - Abigail Alejandro Antenor; Kristine Delica Campang; Khristen Anne Mendoza Rafols; Anastacia Ballesil-Alvarez; Maria Theresa Gusad de Leon; Chris Vincent Jagunap Densing; Rico Jossel Mindoro Maestro; Marc Driz Rosales (TENCON, 2018)

A 2.4 GHz Energy-efficient Short-range Receiver with Wake-up and Multiple Gain Settings for Wireless Sensor Networks. - George Procyon Cabrera; Jhelsea Credo; Gio Ishmael Evidente; Ralen Rose Gloria Malatbalat; Steven Lorenzo Mindoro; Arlo Ricardo Sanico; Anastacia B. Alvarez; Chris Vincent J. Densing; Rico Jossel M. Maestro; Marc D. Rosales; Maria Theresa G. de Leon (TENCON, 2018)

An Ultra-Low Power Direct Active-RF Detection Wake-Up Receiver with Noise-Cancelling Envelope Detector in 65 nm CMOS Process. - Gio Ishmael Evidente; Steven Lorenzo Mindoro; Anastacia B. Alvarez; Chris Vincent J. Densing; Rico Jossel M. Maestro; Marc D. Rosales; Maria Theresa G. de Leon (TENCON, 2018)

A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications. - Fredrick Angelo R. Galapon; Mark Allen D. C. Agaton; Arcel G. Leynes; Lemuel Neil M. Noveno; Anastacia B. Alvarez; Chris Vincent J. Densing; John Richard E. Hizon; Marc D. Rosales; Maria Theresa G. de Leon; Rico Jossel M. Maestro (TENCON, 2018)

Hardware-Based Model of Node Clustering Using Q-Learning for Wireless Sensor Networks. - Gienel Francheska Delos Santos Manarang; Rusty John Lloyd Rodriguez Mina; Mikko Chino Reyes Salvador; Maria Theresa G. de Leon; Chris Vincent Jagunap Densing; Marc Driz Rosales; Anastacia Ballesil-Alvarez (TENCON, 2018)

A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65 nm Technology. - Zyrel Renzo Sanchez; Sam Jason Vasquez; Anastacia B. Alvarez; Chris Vincent J. Densing; John Richard E. Hizon; Rico Jossel M. Maestro; Maria Theresa G. de Leon; Marc D. Rosales (TENCON, 2018)

Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. - Sachin Taneja; Anastacia B. Alvarez; Massimo Alioto (IEEE J. Solid State Circuits, 2018)

Design and Implementation a Self-starting Thermal Energy Harvester with Resonant Startup and Maximum Power Point Tracking Capabilities/or Wireless Sensor Nodes. - Phoebe Laine Panis; Maria Sophia Ralota; Joenard Matanguihan; Anastacia B. Alvarez; John Richard E. Hizon; Marc D. Rosales; Christopher Santos; Maria Theresa G. de Leon (ISOCC, 2019)

A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process. - Fredrick Angelo R. Galapon; Mark Allen D. C. Agaton; Arcel G. Leynes; Lemuel Neil M. Noveno; Anastacia B. Alvarez; Chris Vincent J. Densing; John Richard E. Hizon; Marc D. Rosales; Maria Theresa G. de Leon; Rico Jossel M. Maestro (J. Low Power Electron., 2019)

An Energy-Efficient Temperature Sensor Using CMOS Thyristor Delay Elements. - Ian Christian Fernandez; Maria Theresa G. de Leon; Anastacia B. Alvarez; Marc D. Rosales (ICM, 2020)

A Top-Down Approach for Low Noise Amplifier Design using Verilog-A. - Renzo Nicolas Alsim; Anastacia Ballesil-Alvarez; Maria Theresa G. de Leon; Marc D. Rosales; Maria Patricia Rouelli Sabino-Santos; Christopher Santos; John Richard E. Hizon (ISOCC, 2020)

An Interface for Shock Inputs in Piezoelectric Energy Harvesting using Synchronous Electric Charge Extraction. - Christian Joseph Dia; Ralfael Himor; Anastacia B. Alvarez; John Richard E. Hizon; Marc D. Rosales; Maria Patricia Rouelli Sabino-Santos; Christopher Santos; Maria Theresa G. de Leon (ISOCC, 2020)

5 Gb/s Optical Transceiver for MEMS Tunable HCG-VCSEL in 65 nm CMOS. - Sean Kane Lloyd M. Quintans; Francesca Bea V. Narcida; Janelle Eira A. Tordesillas; Maria Patricia Rouelli G. Sabino; Anastacia B. Alvarez; Maria Theresa G. de Leon; John Richard E. Hizon; Christopher G. Santos; Marc D. Rosales (ISOCC, 2020)

Designing a Class E Power Amplifier through Modeling in Verilog-A. - Arriel Ting; Anastacia B. Alvarez; Maria Theresa G. de Leon; Marc D. Rosales; Maria Patricia Rouelli Sabino-Santos; John Richard E. Hizon; Christopher Santos (ISOCC, 2020)

FPGA-based Features Extraction Sensor for Lettuce Crop. - Maverick Jonas G. Adonis; Renzo S. Forteza; Alaine Richelle C. Ramos; Anastacia B. Alvarez; Maria Theresa G. de Leon; John Richard E. Hizon; Maria Patricia Rouelli Sabino-Santos; Christopher G. Santos; Marc D. Rosales (TENCON, 2020)

Bit-Selection Control for Energy-Efficient Handwritten Digits Recognition Hyperdimensional Computing Architecture. - Ryan Albert G. Antonio; Anastacia B. Alvarez (TENCON, 2020)

Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks. - Michael Joseph Neri; Redentor Immanuel Ridao; Victor Emmanuel Baylosis; Phoebe Meira Chua; Allen Jason Tan; Maria Theresa G. de Leon; John Richard E. Hizon; Marc D. Rosales; Maria Patricia Rouelli Sabino-Santos; Christopher Santos; Anastacia B. Alvarez (TENCON, 2020)

Power and Area Oriented Implementations of Lightweight Cryptographic Algorithms for Wireless Sensor Networks. - Alexis Czezar Cruz Torreno; Maria Theresa Gusad de Leon; Marc Driz Rosales; Anastacia Ballesil-Alvarez (TENCON, 2020)

Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision. - Anastacia B. Alvarez; Gopalakrishnan Ponnusamy; Massimo Alioto (IEEE Access, 2020)

A Voltage-Controlled Magnetic Anisotropy based True Random Number Generator. - Lawrence Roman A. Quizon; Anastacia B. Alvarez; Christoper G. Santos; Marc D. Rosales; John Richard E. Hizon; Maria Patricia Rouelli G. Sabino (ISOCC, 2021)

Redundancy Pruning for Binary Hyperdimensional Computing Architectures. - Ryan Albert G. Antonio; Anastacia B. Alvarez (ISCAS, 2022)

Energy-Efficient Sparse Hyperdimensional Computing for Speech Recognition. - Kim Isaac I. Buelagala; Ginzy S. Javier; Sean Alfred A. Lipardo; James Carlo E. Sorsona; Sherry Joy Alvionne S. Baquiran; Lawrence Roman A. Quizon; Allen Jason Tan; Ryan Albert G. Antonio; Fredrick Angelo R. Galapon; Anastacia B. Alvarez (ISOCC, 2023)

Integration of In-Memory Computing Capabilities to a Self-Matching Complementary-Reference Sensing Scheme for TST-MRAM. - Giussepe Yvanric Galvez; Andrew James Lim; Christopher Jr Camarillo; John Rey Marturillas; Mark Emannuel Teodoro; Ellris Kristian Nuel Urfano; Anastacia B. Alvarez; Ryan Albert G. Antonio; Fredrick Angelo R. Galapon; Sherry Joy Alvionne Baquiran; Allen Jason Tan; Lawrence Roman A. Quizon (ISOCC, 2023)

Federated Learning with MLPerfTiny Tasks and Server-side Momentum. - Lawrence Roman A. Quizon; Anastacia B. Alvarez (ICMLSC, 2024)

A Hyperdimensional Computing Architecture with 4.4x Energy Efficiency in 65nm CMOS. - Fredrick Angelo R. Galapon; Anastacia B. Alvarez (ISCAS, 2024)