Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance. - Dimitrios Garyfallou; Anastasis Vagenas; Charalampos Antoniadis; Yehia Massoud; George I. Stamoulis (ACM Great Lakes Symposium on VLSI, 2022)

Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis. - Georgios Ioannis Paliaroutis; Pelopidas Tsoumanis; Dimitrios Garyfallou; Anastasis Vagenas; Nestoras E. Evmorfopoulos; Georgios I. Stamoulis (DFT, 2023)

Reduction of large-scale RLCk models via low-rank balanced truncation. - Christos Giamouzis; Dimitrios Garyfallou; Anastasis Vagenas; Nestor E. Evmorfopoulos (CoRR, 2023)

Advanced gate-level glitch modeling using ANNs. - Anastasis Vagenas; Dimitrios Garyfallou; Nestor E. Evmorfopoulos; George I. Stamoulis (DAC, 2024)

A learning-based method for performance optimization of timing analysis. - Anastasis Vagenas; Dimitrios Garyfallou; Nestoras E. Evmorfopoulos; George I. Stamoulis (SMACD, 2024)