Verification of FPGA control systems by analyzing the correctness of state diagrams. - Maryna Miroshnyk; Alexander Shkil; Elvira Kulak; Dariia Rakhlis; Inna Filippenko; Anatolii Miroshnyk (DESSERT, 2020)

Assertion Based Design of Timed Finite State Machine. - Alexander Shkil; Anatolii Miroshnyk; Georgiy Kulak; Kyrylo Pshenychnyi (EWDTS, 2021)

Overview of the modern SoC design technologies and open softprocessor architectures. - Maryna Miroshnyk; Inna Filippenko; Valentyn Korniienko; Alexander Shkil; Anatolii Miroshnyk (DESSERT, 2023)

Modeling Faults as Addresses. - Vladimir Hahanov; Ivan Hahanov; Anatolii Miroshnyk; Aleksander Shkil; Dariia Rakhlis; Irina V. Hahanova (EWDTS, 2023)