Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. - Rajiv V. Joshi; S. S. Kang; N. Zamdmar; Anda Mocuta; Ching-Te Chuang; J. A. Pascual-Gutiérrez (VLSI Design, 2005)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. - Geert Eneman; An De Keersgieter; Anda Mocuta; Nadine Collaert; Aaron Thean (ICICDT, 2015)

Modeling FinFET metal gate stack resistance for 14nm node and beyond. - Kenichi Miyaguchi; Bertrand Parvais; Lars-Åke Ragnarsson; Piet Wambacq; Praveen Raghavan; Abdelkarim Mercha; Anda Mocuta; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Nonparabolicity and confinement effects of IIIV materials in novel transistors. - M. Ali Pourghaderi; Anda Mocuta; Aaron Thean (ICICDT, 2015)

I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. - Romain Ritzenthaler; Tom Schram; M. J. Cho; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Christian Caillat; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Assessment of SiGe quantum well transistors for DRAM peripheral applications. - Romain Ritzenthaler; Tom Schram; Geert Eneman; Anda Mocuta; Naoto Horiguchi; Aaron Voon-Yew Thean; Alessio Spessot; Marc Aoulaiche; Pierre Fazan; K. B. Noh; Y. Son (ICICDT, 2015)

Impact of fin shape variability on device performance towards 10nm node. - Kazuyuki Tomida; Keizo Hiraga; Morin Dehan; Geert Hellings; Doyoung Jang; Kenichi Miyaguchi; Thomas Chiarella; Minsoo Kim; Anda Mocuta; Naoto Horiguchi; Abdelkarim Mercha; Diederik Verkest; et al. (ICICDT, 2015)

Towards high performance sub-10nm finW bulk FinFET technology. - Thomas Chiarella; Stefan Kubicek; E. Rosseel; Romain Ritzenthaler; Andriy Hikavyy; P. Eyben; An De Keersgieter; L.-Å. Ragnarsson; M.-S. Kim; S.-A. Chew; Tom Schram; S. Demuynck; et al. (ESSDERC, 2016)

Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors. - Devin Verreck; Anne S. Verhulst; Bart Soree; Nadine Collaert; Anda Mocuta; Aaron Thean; Guido Groeseneken (ESSDERC, 2016)

On the ballistic ratio in 14nm-Node FinFETs. - Fabian M. Bufler; Kenichi Miyaguchi; Thomas Chiarella; N. Horiguchi; Anda Mocuta (ESSDERC, 2017)

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Dmitry Yakimets; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ESSDERC, 2017)

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ICICDT, 2017)

SRAM designs for 5nm node and beyond: Opportunities and challenges. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Alessio Spessot; Diederik Verkest; Anda Mocuta (ICICDT, 2017)

New methodology for modelling MOL TDDB coping with variability. - Philippe J. Roussel; Adrian Vaisman Chasin; Steven Demuynck; Naoto Horiguchi; Dimitri Linten; Anda Mocuta (IRPS, 2018)

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. - Trong Huynh Bao; Anabela Veloso; Sushil Sakhare; Philippe Matagne; Julien Ryckaert; Manu Perumkunnil; Davide Crotti; Farrukh Yasin; Alessio Spessot; Arnaud Furnémont; Gouri Sankar Kar; Anda Mocuta (DAC, 2019)

CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. - Shih-Hung Chen; Dimitri Linten; Geert Hellings; Marko Simicic; Ben Kaczer; Thomas Chiarella; Hans Mertens; Jérôme Mitard; Anda Mocuta; N. Horiguchi (IRPS, 2019)