Testability Properties of Vertex Precedent BDDs. - André Inácio Reis; A. Prado; Marcelo Lubaszewski (SBCCI, 2000)

A Tutorial Tool for Switch Logic. - Vinícius P. Correia; André Inácio Reis (MSE, 2001)

Concepção de Circuitos e Sistemas Integrados. - Renato P. Ribas; André Inácio Reis; Marcelo Lubaszewski (RITA, 2001)

Comparing Transistor-Level Implementations of 4-Input Logic Functions. - Felipe Ribeiro Schneider; Vinícius P. Correia; Renato P. Ribas; André Inácio Reis (IWLS, 2002)

Testability Properties of BDDs. - Felipe S. Marques 001; Vinícius P. Correia; A. Prado; Marcelo Lubaszewski; André Inácio Reis (SBCCI, 2002)

Compression and Technology Mapping of Logic Circuits. - Vinícius Pazutti Correia; André Inácio Reis (SBCCI, 2002)

Automatic Generation of Digital Cell Libraries. - João Daniel Togni; Felipe Ribeiro Schneider; Vinícius P. Correia; Renato P. Ribas; André Inácio Reis (SBCCI, 2002)

SIFU! - A Didactic Stuck-at Fault Simulator. - Vinícius P. Correia; Marcelo Lubaszewski; André Inácio Reis (MSE, 2003)

Scheduling Policy Costs on a JAVA Microcontroller. - Leomar S. da Rosa Jr.; Flávio Rech Wagner; Luigi Carro; Alexandre Carissimi; André Inácio Reis (OTM Workshops, 2003)

Unified Theory to Build Cell-Level Transistor Networks from BDDs. - Renato E. B. Poli; Felipe Ribeiro Schneider; Renato P. Ribas; André Inácio Reis (SBCCI, 2003)

Advanced technology mapping for standard-cell generators. - Vinícius P. Correia; André Inácio Reis (SBCCI, 2004)

Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. - Mário C. B. Osorio; Carlos A. Sampaio; André Inácio Reis; Renato P. Ribas (SBCCI, 2004)

A new approach to the use of satisfiability in false path detection. - Felipe S. Marques 001; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2005)

Tool integration using the web-services approach. - João Daniel Togni; Renato P. Ribas; Maria Lúcia Blanck Lisbôa; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2005)

Exact lower bound for the number of switches in series to implement a combinational logic cell. - Felipe Ribeiro Schneider; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (ICCD, 2005)

Asynchronous circuit design on reconfigurable devices. - R. U. R. Mocho; G. H. Sartori; Renato P. Ribas; André Inácio Reis (SBCCI, 2006)

Fast disjoint transistor networks from BDDs. - Leomar S. da Rosa Jr.; Felipe S. Marques 001; Tiago Muller Gil Cardoso; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (SBCCI, 2006)

Modeling and estimating leakage current in series-parallel CMOS networks. - Paulo F. Butzen; André Inácio Reis; Chris H. Kim; Renato P. Ribas (ACM Great Lakes Symposium on VLSI, 2007)

DAG based library-free technology mapping. - Felipe S. Marques 001; Leomar S. da Rosa Jr.; Renato P. Ribas; Sachin S. Sapatnekar; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2007)

Modeling Subthreshold Leakage Current in General Transistor Networks. - Paulo F. Butzen; André Inácio Reis; Chris H. Kim; Renato P. Ribas (ISVLSI, 2007)

KARMA: A Didactic Tool for Two-Level Logic Synthesis. - Carlos Eduardo Klock; Felipe Ribeiro Schneider; M. V. N. Gomes; Dionatan S. Moura; Renato P. Ribas; André Inácio Reis (MSE, 2007)

Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. - Paulo F. Butzen; André Inácio Reis; Chris H. Kim; Renato P. Ribas (PATMOS, 2007)

A comparative study of CMOS gates with minimum transistor stacks. - Leomar S. da Rosa Jr.; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Felipe Ribeiro Schneider (SBCCI, 2007)

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. - Paulo F. Butzen; Leomar S. da Rosa Jr.; Erasmo J. D. Chiappetta Filho; Dionatan S. Moura; André Inácio Reis; Renato P. Ribas (ACM Great Lakes Symposium on VLSI, 2008)

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. - Tiago Muller Gil Cardoso; Leomar S. da Rosa Jr.; Felipe de Souza Marques; Renato P. Ribas; André Inácio Reis (ISQED, 2008)

Efficient Test Circuit to Qualify Logic Cells. - Renato P. Ribas; Simone Bavaresco; Marcelo Lubaszewski; André Inácio Reis (ISCAS, 2009)

Switch level optimization of digital CMOS gate networks. - Leomar S. da Rosa Jr.; Felipe Ribeiro Schneider; Renato P. Ribas; André Inácio Reis (ISQED, 2009)

Routing Resistance Influence in Loading Effect on Leakage Analysis. - Paulo F. Butzen; André Inácio Reis; Renato P. Ribas (PATMOS, 2009)

What about the IP of your IP?: an introduction to intellectual property law for engineers and scientists. - André Inácio Reis; Roner G. Fabris (SBCCI, 2009)

CMOS logic gate performance variability related to transistor network arrangements. - Digeorgia N. da Silva; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2009)

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. - Osvaldo Martinello; Felipe S. Marques 001; Renato P. Ribas; André Inácio Reis (DATE, 2010)

Boolean factoring with multi-objective goals. - Mayler G. A. Martins; Leomar S. da Rosa Jr.; Anders B. Rasmussen; Renato P. Ribas; André Inácio Reis (ICCD, 2010)

SwitchCraft: a framework for transistor network design. - Vinicius Callegaro; Felipe de Souza Marques; Carlos Eduardo Klock; Leomar Soares da Rosa Jr.; Renato P. Ribas; André Inácio Reis (SBCCI, 2010)

Improvements on the detection of false paths by using unateness and satisfiability. - Felipe S. Marques 001; Osvaldo Martinello; Renato P. Ribas; André Inácio Reis (SBCCI, 2010)

Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. - Paulo F. Butzen; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (J. Low Power Electron., 2010)

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. - Paulo F. Butzen; Leomar S. da Rosa Jr.; Erasmo J. D. Chiappetta Filho; André Inácio Reis; Renato P. Ribas (Microelectron. J., 2010)

Transistor network restructuring against NBTI degradation. - Paulo F. Butzen; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2010)

Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology. - Digeorgia N. da Silva; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2010)

Karma: um ambiente para o aprendizado de síntese de funções Booleanas. - Carlos Eduardo Klock; Renato Perez Ribas; André Inácio Reis (Revista Brasileira de Informática na Educ., 2010)

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. - Martin Elhøj; André Inácio Reis; Renato P. Ribas; Fabrizio Ferrandi; Christian Pilato; Francesc Moll; Miguel Miranda; Petr Dobrovolný; Nigel Woolaway; Arnaud Grasset; Philippe Bonnot 001; Giuseppe Desoli; et al. (ARCS Workshops, 2011)

Constructive AIG optimization through functional composition. - Thiago Figueiro; Renato P. Ribas; André Inácio Reis (ARCS Workshops, 2011)

Transistor Sizing Analysis of Regular Fabrics. - Felipe S. Marranghello; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas; Francesc Moll (ARCS Workshops, 2011)

Efficient method to compute minimum decision chains of Boolean functions. - Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (ACM Great Lakes Symposium on VLSI, 2011)

Impact and optimization of lithography-aware regular layout in digital circuit design. - Vinícius Dal Bem; Paulo F. Butzen; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ICCD, 2011)

Performance and functional test of flip-flops using ring oscillator structure. - Renato P. Ribas; André Inácio Reis; André Ivanov (IDT, 2011)

Self-checking test circuits for latches and flip-flops. - Renato P. Ribas; Yuyang Sun; André Inácio Reis; André Ivanov (IOLTS, 2011)

Constructive AIG optimization considering input weights. - Thiago Figueiro; Renato P. Ribas; André Inácio Reis (ISQED, 2011)

Area impact analysis of via-configurable regular fabric for digital integrated circuit design. - Vinícius Dal Bem; Paulo F. Butzen; Carlos Eduardo Klock; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (SBCCI, 2011)

Transistor sizing in lithography-aware regular fabrics. - Felipe S. Marranghello; Vinícius Dal Bem; André Inácio Reis; Francesc Moll; Renato P. Ribas (SBCCI, 2011)

Ring oscillators for functional and delay test of latches and flip-flops. - Renato P. Ribas; Yuyang Sun; André Inácio Reis; André Ivanov (SBCCI, 2011)

Contributions to the evaluation of ensembles of combinational logic gates. - Renato P. Ribas; Simone Bavaresco; N. Schuch; Vinicius Callegaro; Marcelo Lubaszewski; André Inácio Reis (Microelectron. J., 2011)

Functional composition: A new paradigm for performing logic synthesis. - Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (ISQED, 2012)

Lithography analysis of via-configurable transistor-array fabrics. - Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (NORCHIP, 2012)

KL-cut based digital circuit remapping. - Lucas Machado; Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (NORCHIP, 2012)

Design-oriented delay model for CMOS inverter. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (SBCCI, 2012)

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (SBCCI, 2012)

Design of CMOS logic gates with enhanced robustness against aging degradation. - Paulo F. Butzen; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2012)

Efficient transistor-level design of CMOS gates. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (ACM Great Lakes Symposium on VLSI, 2013)

CMOS inverter delay model based on DC transfer curve for slow input. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ISQED, 2013)

Logic synthesis for manufacturability considering regularity and lithography printability. - Lucas Machado; Vinícius Dal Bem; Francesc Moll; Sergio Gómez; Renato P. Ribas; André Inácio Reis (ISVLSI, 2013)

Iterative remapping respecting timing constraints. - Lucas Machado; Mayler G. A. Martins; Vinicius Callegaro; Renato P. Ribas; André Inácio Reis (ISVLSI, 2013)

Transistor-level optimization of CMOS complex gates. - Vinicius N. Possani; Felipe S. Marques 001; Leomar S. da Rosa Jr.; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (LASCAS, 2013)

Analytical logical effort formulation for minimum active area under delay constraints. - Caio G. P. Alegretti; Vinícius Dal Bem; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

Read-polarity-once Boolean functions. - Vinicius Callegaro; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

Delay model for static CMOS complex gates. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (SBCCI, 2013)

Spin diode network synthesis using functional composition. - Mayler G. A. Martins; Felipe S. Marranghello; Joseph S. Friedman; Alan V. Sahakian; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

Synthesis of threshold logic gates to nanoelectronics. - Augusto Neutzling; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (SBCCI, 2013)

A methodology to evaluate the aging impact on flip-flops performance. - Cicero Nunes; Paulo F. Butzen; André Inácio Reis; Renato P. Ribas (SBCCI, 2013)

Improving the methodology to build non-series-parallel transistor arrangements. - Vinicius N. Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (SBCCI, 2013)

Power consumption analysis in static CMOS gates. - Alberto Wiltgen; Kim A. Escobar; André Inácio Reis; Renato P. Ribas (SBCCI, 2013)

BTI and HCI first-order aging estimation for early use in standard cell technology mapping. - Paulo F. Butzen; Vinícius Dal Bem; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2013)

BTI, HCI and TDDB aging impact in flip-flops. - Cicero Nunes; Paulo F. Butzen; André Inácio Reis; Renato P. Ribas (Microelectron. Reliab., 2013)

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? - Matheus T. Moreira; Augusto Neutzling; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas; Ney Calazans (ASYNC, 2014)

CMOS inverter analytical delay model considering all operating regions. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ISCAS, 2014)

A constructive approach for threshold logic circuit synthesis. - Augusto Neutzling; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (ISCAS, 2014)

Methodology for achieving best trade-off of area and fault masking coverage in ATMR. - Iuri A. C. Gomes; Mayler G. A. Martins; Fernanda Lima Kastensmidt; André Inácio Reis; Renato P. Ribas; Sylvain P. Novales (LATW, 2014)

Optimization on cell-library design for digital Application Specific Printed Electronics Circuits. - Manuel Llamas; Mohammad Mashayekhi; Jordi Carrabina; Jody Maick Matos; André Inácio Reis (PATMOS, 2014)

Deriving Reduced Transistor Count Circuits from AIGs. - Jody Maick Matos; Marcus Ritt; Renato P. Ribas; André Inácio Reis (SBCCI, 2014)

Exploring Independent Gates in FinFET-Based Transistor Network Generation. - Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar Soares da Rosa Jr. (SBCCI, 2014)

Enhanced Spin-Diode Synthesis Using Logic Sharing. - Mayler G. A. Martins; Felipe S. Marranghello; Joseph S. Friedman; Alan V. Sahakian; Renato P. Ribas; André Inácio Reis (DSD, 2015)

Threshold Logic Synthesis Based on Cut Pruning. - Augusto Neutzling; Jody Maick Matos; André Inácio Reis; Renato P. Ribas; Alan Mishchenko (ICCAD, 2015)

Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. - Vinicius Callegaro; Felipe S. Marranghello; Mayler G. A. Martins; Renato P. Ribas; André Inácio Reis (ICCD, 2015)

SOP based logic synthesis for memristive IMPLY stateful logic. - Felipe S. Marranghello; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (ICCD, 2015)

Improved logic synthesis for memristive stateful logic using multi-memristor implication. - Felipe S. Marranghello; Vinicius Callegaro; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas (ISCAS, 2015)

Fast buffer delay estimation considering time-dependent dielectric breakdown. - Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (ISCAS, 2015)

Open Cell Library in 15nm FreePDK Technology. - Mayler G. A. Martins; Jody Maick Matos; Renato P. Ribas; André Inácio Reis; Guilherme Schlinker; Lucio Rech; Jens Michelsen (ISPD, 2015)

A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design. - Jody Maick Matos; Augusto Neutzling; Renato P. Ribas; André Inácio Reis (ISPD, 2015)

Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. - Iuri A. C. Gomes; Mayler G. A. Martins; André Inácio Reis; Fernanda Lima Kastensmidt (LATS, 2015)

Factored Forms for Memristive Material Implication Stateful Logic. - Felipe S. Marranghello; Vinicius Callegaro; Mayler G. A. Martins; André Inácio Reis; Renato P. Ribas (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. - Iuri A. C. Gomes; Mayler G. A. Martins; André Inácio Reis; Fernanda Lima Kastensmidt (Microelectron. Reliab., 2015)

Performance evaluation of optimized transistor networks built using independent-gate FinFET. - Andres M. A. Valdes; Vinicius N. Possani; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (LASCAS, 2016)

Graph-Based Transistor Network Generation Method for Supergate Design. - Vinicius Neves Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Contributions to Modeling Patent Claims When Representing Patent Knowledge. - Simone R. N. Reis; André Inácio Reis; Jordi Carrabina; Pompeu Casanovas (AICOL, 2017)

Fast-extract with cube hashing. - Bruno de O. Schmitt; Alan Mishchenko; Victor N. Kravets; Robert K. Brayton; André Inácio Reis (ASP-DAC, 2017)

Binary adder circuit design using emerging MIGFET devices. - Jeferson José Baqueta; Felipe S. Marranghello; Vinicius N. Possani; Augusto Neutzling; André Inácio Reis; Renato P. Ribas (ISQED, 2017)

Transistor Count Optimization in IG FinFET Network Design. - Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques 001; Leomar S. da Rosa Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. - Vinícius Dal Bem; Felipe S. Marranghello; André Inácio Reis; Renato P. Ribas (IEEE Trans. Emerg. Top. Comput., 2017)

Physical Awareness Starting at Technology-Independent Logic Synthesis. - André Inácio Reis; Jody M. A. Matos (Advanced Logic Synthesis, 2018)

Unlocking fine-grain parallelism for AIG rewriting. - Vinicius N. Possani; Yi-Shan Lu; Alan Mishchenko; Keshav Pingali; Renato P. Ribas; André Inácio Reis (ICCAD, 2018)

Technology Mapping for Circuits with Simple Cells. - Jody Maick Matos; André Inácio Reis; Jordi Carrabina (ISCAS, 2018)

Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution. - André Inácio Reis (ISPD, 2018)

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; André Inácio Reis; Renato P. Ribas (SBCCI, 2018)

A Simple and Effective Heuristic Method for Threshold Logic Identification. - Augusto Neutzling; Mayler G. A. Martins; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Reduction of neural network circuits by constant and nearly constant signal propagation. - Augusto Andre Souza Berndt; Alan Mishchenko; Paulo Francisco Butzen; André Inácio Reis (SBCCI, 2019)

Efficiently Mapping VLSI Circuits With Simple Cells. - Jody Maick Matos; Jordi Carrabina; André Inácio Reis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Effective Logic Synthesis for Threshold Logic Circuit Design. - Augusto Neutzling; Jody Maick Matos; Alan Mishchenko; André Inácio Reis; Renato P. Ribas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Four-Level Forms for Memristive Material Implication Logic. - Felipe S. Marranghello; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Exact Benchmark Circuits for Logic Synthesis. - Walter Lau Neto; Vinicius N. Possani; Felipe S. Marranghello; Jody Maick Matos; Pierre-Emmanuel Gaillardon; André Inácio Reis; Renato Perez Ribas (IEEE Des. Test, 2020)

maj-n Logic Synthesis for Emerging Technology. - Augusto Neutzling; Felipe S. Marranghello; Jody Maick Matos; André Inácio Reis; Renato P. Ribas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Parallel Combinational Equivalence Checking. - Vinicius N. Possani; Alan Mishchenko; Renato P. Ribas; André Inácio Reis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Possible Reductions to Generate circuits from BDDs. - Eduarde D. Brandão; Joao P. Nespolo; Renato D. Peralta; Paulo F. Butzen; André Inácio Reis (ISVLSI, 2022)

A Virtual Board Approach for Prototyping and Teaching Digital Design. - Alcides S. Costa; Leonardo Droves Silveira; André Inácio Reis (SBCCI, 2022)

Optimizing machine learning logic circuits with constant signal propagation. - Augusto Andre Souza Berndt; Cristina Meinhardt; André Inácio Reis; Paulo F. Butzen (Integr., 2022)

Live Demonstration: Pitanga Platform for Virtual FPGA Remote Laboratories. - Alcides S. Costa; Leonardo Droves Silveira; André Inácio Reis (ISCAS, 2023)

An Improved method to join BDDs for incompletely specified Boolean functions. - Renato D. Peralta; Joao P. Nespolo; Paulo F. Butzen; Mariana Kolberg; André Inácio Reis (ISCAS, 2023)

Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis. - Gabriel Ammes; Paulo F. Butzen; André Inácio Reis; Renato P. Ribas (ISVLSI, 2023)

ATMR design by construction based on two-level ALS. - Gabriel Ammes; Guilherme B. Manske; Paulo F. Butzen; André Inácio Reis; Renato P. Ribas (SBCCI, 2023)

Effect of Unique Table Implementation in the Performance of BDD Packages. - Joao P. Nespolo; Renato D. Peralta; Paulo F. Butzen; André Inácio Reis (SBCCI, 2023)

Extending Multilevel ALS to Design ATMRs. - Gabriel Ammes; Guilherme B. Manske; Paulo F. Butzen; André Inácio Reis; Renato P. Ribas (LASCAS, 2024)