DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code. - H. Gregor Molter; André Seffrin; Sorin Alexander Huss (FDL, 2009)

Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes. - André Seffrin; Alexander Biedermann; Sorin A. Huss (FDL, 2010)

A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capability. - André Seffrin; Sunil Malipatlolla; Sorin A. Huss (FPT, 2010)

Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms. - André Seffrin; Sorin A. Huss (DDECS, 2011)

Hardware-accelerated execution of Pi-calculus reconfiguration schedules. - André Seffrin; Sorin A. Huss (FPT, 2011)

Determining Minimum Interconnect for Reconfigurable Hardware by Analysis and Verification of Pi-Calculus Design Specifications. - André Seffrin; Sorin A. Huss (MBMV, 2011)

Ensuring Secure Information Flow in Partially Reconfigurable Architectures by Means of Process Algebra Analysis. - André Seffrin; Sorin A. Huss (TrustCom, 2011)

State space optimization within the DEVS model of computation for timing efficiency. - H. Gregor Molter; André Seffrin; Sorin A. Huss (VLSI-SoC, 2011)

Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only). - André Seffrin; Sorin A. Huss (FPGA, 2012)

Bil: A tool-chain for bitstream reverse-engineering. - Florian Benz; André Seffrin; Sorin A. Huss (FPL, 2012)

A Process-Algebraic Approach to Security-Aware Scheduling of Dynamic Partial Reconfiguration on FPGA Devices. - André Seffrin (Verlag Dr. Hut, 2012)