Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Roberto Nonis; Pierpaolo Palestri (APCCAS, 2016)

Design of a transmitter for high-speed serial interfaces in automotive micro-controller. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Roberto Nonis; Pierpaolo Palestri (MIPRO, 2016)

Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Matteo Bassi; Roberto Nonis; Pierpaolo Palestri (ISCAS, 2018)

Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes. - Martino Dazzi; Pierpaolo Palestri; Davide Rossi; Andrea Bandiziol; Igor Loi; David E. Bellasi; Luca Benini (ISCAS, 2018)

A CMOS Pixelated Nanocapacitor Biosensor Platform for High-Frequency Impedance Spectroscopy and Imaging. - Frans Widdershoven; Andrea Cossettini; Cecilia Laborde; Andrea Bandiziol; Paul P. van Swinderen; Serge G. Lemay; Luca Selmi (IEEE Trans. Biomed. Circuits Syst., 2018)

Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE. - Andrea Bandiziol; Werner Grollitsch; Giovanni Steffan; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers. - Dylan D'Ampolo; Andrea Bandiziol; Davide Menin; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (APCCAS, 2019)

A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces. - Alessio Cortiula; Martino Dazzi; Mattia Marcon; Davide Menin; Marco Scapol; Andrea Bandiziol; Andrea Cristofoli; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (MIPRO, 2019)

Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications. - Davide Menin; Andrea Bandiziol; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation. - Pierpaolo Palestri; Ahmed Elnaqib; Davide Menin; Klaid Shyti; Francesco Brandonisio; Andrea Bandiziol; Davide Rossi; Roberto Nonis (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces. - Alessio Cortiula; Davide Menin; Andrea Bandiziol; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)