System analysis and circuit design of CMOS integrated wireless receivers for WCDMA and UWB applications. - Andrea Bevilacqua (2003)

An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers. - Andrea Bevilacqua; Ali M. Niknejad (IEEE J. Solid State Circuits, 2004)

Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers. - Andrea Bevilacqua; Francesco Svelto (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection. - Andrea Bevilacqua; Andrea Maniero; Andrea Gerosa; Andrea Neviani (ICECS, 2006)

A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency. - Andrea Maniero; Andrea Bevilacqua; Andrea Gerosa; Andrea Neviani (ICECS, 2006)

An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter. - Andrea Gerosa; Andrea Bevilacqua; Andrea Neviani; Andrea Xotta (ISCAS, 2006)

An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Sigma Delta Modulator and a Flash Converter. - Andrea Gerosa; Andrea Xotta; Andrea Bevilacqua; Andrea Neviani (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 μm CMOS. - Alessio Vallese; Andrea Bevilacqua; Christoph Sandner; Marc Tiebout; Andrea Gerosa; Andrea Neviani (ESSCIRC, 2007)

Quadrature VCOs Based on Coupled PLLs. - Andrea Bevilacqua; Christoph Sandner; Andrea Gerosa; Andrea Neviani (ISCAS, 2007)

A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers. - Andrea Bevilacqua; Alessio Vallese; Christoph Sandner; Marc Tiebout; Andrea Gerosa; Andrea Neviani (ISSCC, 2007)

An Integrated Solution for Suppressing WLAN Signals in UWB Receivers. - Andrea Bevilacqua; Andrea Maniero; Andrea Gerosa; Andrea Neviani (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Transformer-Based Dual-Mode Voltage-Controlled Oscillators. - Andrea Bevilacqua; Federico P. Pavan; Christoph Sandner; Andrea Gerosa; Andrea Neviani (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Design of broadband inductorless LNAs in ultra-scaled CMOS technologies. - Andrea Bevilacqua; Matteo Camponeschi; Marc Tiebout; Andrea Gerosa; Andrea Neviani (ISCAS, 2008)

An energy-detector for non-coherent impulse-radio UWB receivers. - Andrea Gerosa; Maurizio Dalla Costa; Andrea Bevilacqua; Daniele Vogrig; Andrea Neviani (ISCAS, 2008)

Analog decoding of trellis coded modulation for multi-level flash memories. - Silvia Soldà; Daniele Vogrig; Andrea Bevilacqua; Andrea Gerosa; Andrea Neviani (ISCAS, 2008)

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. - Jonathan Borremans; Andrea Bevilacqua; Stephane Bronckers; Morin Dehan; Maarten Kuijk; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2008)

UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. - Stefano Dal Toso; Andrea Bevilacqua; Marc Tiebout; Stefano Marsili; Christoph Sandner; Andrea Gerosa; Andrea Neviani (IEEE J. Solid State Circuits, 2008)

A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. - Stefano Dal Toso; Andrea Bevilacqua; Marc Tiebout; Nicola Da Dalt; Andrea Gerosa; Andrea Neviani (ESSCIRC, 2009)

Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems. - Alessio Vallese; Andrea Bevilacqua; Christoph Sandner; Marc Tiebout; Andrea Gerosa; Andrea Neviani (IEEE J. Solid State Circuits, 2009)

An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers. - Andrea Gerosa; Silvia Soldà; Andrea Bevilacqua; Daniele Vogrig; Andrea Neviani (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. - Andrea Bevilacqua; Leonardo Lorenzon; Nicola Da Dalt; Andrea Gerosa; Andrea Neviani (ESSCIRC, 2010)

A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request. - Silvia Soldà; Michele Caruso; Andrea Bevilacqua; Andrea Gerosa; Daniele Vogrig; Andrea Neviani (ESSCIRC, 2010)

Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end. - Matteo Camponeschi; Andrea Bevilacqua; Andrea Neviani; Pietro Andreani (ISCAS, 2010)

A digitally programmable ring oscillator in the UWB range. - Andrea Gerosa; Silvia Soldà; Andrea Bevilacqua; Daniele Vogrig; Andrea Neviani (ISCAS, 2010)

Low-power UWB transmitter using a combined mixer and power amplifier. - Silvia Soldà; Michele Caruso; Daniele Vogrig; Andrea Bevilacqua; Andrea Gerosa; Andrea Neviani (ISCAS, 2010)

A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks. - Stefano Dal Toso; Andrea Bevilacqua; Andrea Gerosa; Andrea Neviani (ISCAS, 2010)

A 0.06 mm 2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS. - Stefano Dal Toso; Andrea Bevilacqua; Marc Tiebout; Nicola Da Dalt; Andrea Gerosa; Andrea Neviani (IEEE J. Solid State Circuits, 2010)

Integrated transceivers for UWB breast cancer imaging: Architecture and circuit constraints. - Matteo Bassi; Andrea Bevilacqua; Andrea Gerosa; Andrea Neviani (ISCAS, 2011)

On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory. - Andrea Bevilacqua; Pietro Andreani (ISCAS, 2011)

A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2. - Andrea Bevilacqua; Pietro Andreani (NORCHIP, 2011)

A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 μm CMOS. - Silvia Soldà; Michele Caruso; Andrea Bevilacqua; Andrea Gerosa; Daniele Vogrig; Andrea Neviani (IEEE J. Solid State Circuits, 2011)

A 1.75-15 GHz stepped frequency receiver for breast cancer imaging in 65 nm CMOS. - Matteo Bassi; Michele Caruso; Andrea Bevilacqua; Andrea Neviani (ESSCIRC, 2012)

A SiGe bipolar VCO for backhaul E-band communication systems. - Fabio Padovan; Marc Tiebout; Koen L. R. Mertens; Andrea Bevilacqua; Andrea Neviani (ESSCIRC, 2012)

Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications. - Andrea Neviani; Andrea Bevilacqua; Andrea Gerosa; Daniele Vogrig (ICICDT, 2012)

Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints. - Matteo Bassi; Andrea Bevilacqua; Andrea Gerosa; Andrea Neviani (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator. - Andrea Bevilacqua; Pietro Andreani (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators. - Andrea Bevilacqua; Pietro Andreani (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Wideband 2-16GHz local oscillator generation for short-range radar applications. - Michele Caruso; Matteo Bassi; Andrea Bevilacqua; Andrea Neviani (ESSCIRC, 2013)

A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOS. - Michele Caruso; Matteo Bassi; Andrea Bevilacqua; Andrea Neviani (ISSCC, 2013)

A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer. - Matteo Bassi; Michele Caruso; Andrea Bevilacqua; Andrea Neviani (IEEE J. Solid State Circuits, 2013)

A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS. - Fabio Padovan; Andrea Bevilacqua; Andrea Neviani (ESSCIRC, 2014)

A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP. - Junlei Zhao; Matteo Bassi; Andrea Bevilacqua; Andrea Ghilioni; Andrea Mazzanti; Francesco Svelto (ESSCIRC, 2014)

Energy-efficient ultra-wideband impulse radios for short-range low-data rate communications. - Andrea Bevilacqua; Andrea Neviani (ICECS, 2014)

A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation. - Fabio Padovan; Marc Tiebout; Andrea Neviani; Andrea Bevilacqua (ESSCIRC, 2015)

Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs. - Antonio Passamani; Davide Ponton; Gerhard Knoblinger; Andrea Bevilacqua (NORCAS, 2015)

A 40-67 GHz Power Amplifier With 13 dBm ℙSAT and 16% PAE in 28 nm CMOS LP. - Matteo Bassi; Junlei Zhao; Andrea Bevilacqua; Andrea Ghilioni; Andrea Mazzanti; Francesco Svelto (IEEE J. Solid State Circuits, 2015)

A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications. - Michele Caruso; Matteo Bassi; Andrea Bevilacqua; Andrea Neviani (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators. - Andrea Mazzanti; Andrea Bevilacqua (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation. - Fabio Padovan; Marc Tiebout; Koen L. R. Mertens; Andrea Bevilacqua; Andrea Neviani (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers. - Fabio Padovan; Marc Tiebout; Andrea Neviani; Andrea Bevilacqua (ESSCIRC, 2016)

A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation. - Fabio Padovan; Marc Tiebout; Andrea Neviani; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2016)

A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. - Stefano Brenna; Fabio Padovan; Andrea Neviani; Andrea Bevilacqua; Andrea Bonfanti; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset. - Fabio Boscolo; Fabio Padovan; Fabio Quadrelli; Marc Tiebout; Andrea Neviani; Andrea Bevilacqua (ESSCIRC, 2017)

Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems. - Paolo Scaramuzza; Carlo Rubino; Marc Tiebout; Michele Caruso; Markus Ortner; Andrea Neviani; Andrea Bevilacqua (ESSCIRC, 2017)

13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE. - Antonio Passamani; Davide Ponton; Edwin Thaller; Gerhard Knoblinger; Andrea Neviani; Andrea Bevilacqua (ISSCC, 2017)

Analyzing Complex Models Using Data and Statistics. - Abani K. Patra; Andrea Bevilacqua; Ali Akhavan-Safaei (ICCS (2), 2018)

A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner. - Antonio Passamani; Davide Ponton; Andreas Wolter; Gerhard Knoblinger; Andrea Bevilacqua (ICECS, 2018)

A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations. - Fabio Padovan; Fabio Quadrelli; Matteo Bassi; Marc Tiebout; Andrea Bevilacqua (ISSCC, 2018)

Session 23 overview: LO generation: RF subcommittee. - Hyunchol Shin; Andrea Bevilacqua; Piet Wambacq (ISSCC, 2018)

Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC). - Andrea Bevilacqua; Shidhartha Das; Pieter Harpe (IEEE J. Solid State Circuits, 2018)

On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators. - Alessandro Franceschin; Fabio Padovan; Roberto Nonis; Andrea Bevilacqua (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks. - Andrea Mazzanti; Andrea Bevilacqua (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

On the Remarkable Performance of the Series-Resonance CMOS Oscillator. - Federico Pepe; Andrea Bevilacqua; Pietro Andreani (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique. - Paolo Scaramuzza; Carlo Rubino; Michele Caruso; Marc Tiebout; Andrea Bevilacqua; Andrea Neviani (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS. - Andrea Bilato; Vadim Issakov; Andrea Bevilacqua (BCICTS, 2019)

A 17 GHz All-npn Push-Pull Class-C VCO. - Simone Veni; Michele Caruso; Marc Tiebout; Andrea Bevilacqua (BCICTS, 2019)

A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS. - Matteo Bassi; Giovanni Boi; Fabio Padovan; Jonas Fritzin; Stefano Di Martino; Daniel Knauder; Andrea Bevilacqua (ESSCIRC, 2019)

A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion. - Alessandro Franceschin; Pietro Andreani; Fabio Padovan; Matteo Bassi; Roberto Nonis; Andrea Bevilacqua (ESSCIRC, 2019)

A 130-nm CMOS Dual Input-Polarity DC-DC Converter for Low-Power Applications. - Alberto Gatti; Giorgio Spiazzi; Andrea Gerosa; Andrea Neviani; Andrea Bevilacqua (ESSCIRC, 2019)

Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters. - Gianluca Marin; Kyrylo Cherniak; Volha Subotskaya; Emanuele Bodano; Christoph Sandner; Andrea Bevilacqua (ICECS, 2019)

A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology. - Andrea Gerosa; Andrea Bevilacqua; Giorgio Spiazzi (ISCAS, 2019)

Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters. - Gianluca Marin; Kyrylo Cherniak; Volha Subotskaya; Emanuele Bodano; Christoph Sandner; Andrea Bevilacqua (ISCAS, 2020)

A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects. - Alessandro Franceschin; Pietro Andreani; Fabio Padovan; Matteo Bassi; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2020)

Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO. - Simone Veni; Pietro Andreani; Michele Caruso; Marc Tiebout; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2020)

A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS. - Davide Manente; Fabio Quadrelli; Fabio Padovan; Matteo Bassi; Andrea Mazzanti; Andrea Bevilacqua (ESSCIRC, 2021)

Session 20 Overview: High-Performance VCOs Rf Subcommittee. - Andrea Bevilacqua; Salvatore Levantino; Hua Wang (ISSCC, 2021)

Doubly-Tuned Transformer Networks: A Tutorial. - Andrea Bevilacqua; Andrea Mazzanti (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Andrea Bevilacqua; Luca Bertulessi; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; et al. (CICC, 2022)

A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS. - Agata Iesurum; Davide Manente; Fabio Padovan; Matteo Bassi; Andrea Bevilacqua (ESSCIRC, 2022)

A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea Leonardo Lacaita; et al. (ISSCC, 2022)

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2022)

A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications. - Fabio Quadrelli; Davide Manente; David Seebacher; Fabio Padovan; Matteo Bassi; Andrea Mazzanti; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2022)

A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise. - Lorenzo Tomasin; Pietro Andreani; Giovanni Boi; Fabio Padovan; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2022)

A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem. - Lorenzo Tomasin; Andrea Bevilacqua (PRIME, 2023)

On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies. - Nicolò Zugno; Francesco Brandonisio; Thomas Niederfriniger; Andrea Bevilacqua (PRIME, 2023)

A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures. - Davide Manente; Fabio Quadrelli; Fabio Padovan; Matteo Bassi; Andrea Mazzanti; Andrea Bevilacqua (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2023)

On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting. - Luca Bellemo; Giorgio Spiazzi; Andrea Bevilacqua (NorCAS, 2024)

On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers. - Edoardo Baiesi Fietta; David Seebacher; Davide Ponton; Andrea Bevilacqua (NorCAS, 2024)

On the Efficiency of Output-Matched Radiofrequency Power Amplifiers. - Davide Pecile; Stefan Kokorovic; Alberto Gambarucci; Andrea Bevilacqua (PRIME, 2024)

Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology. - Nicolò Zugno; Andrea Bevilacqua (PRIME, 2024)

Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs. - Agata Iesurum; Davide Manente; Fabio Padovan; Matteo Bassi; Andrea Bevilacqua (IEEE J. Solid State Circuits, 2024)

ELICIPY 1.0: A Python online tool for expert elicitation. - Mattia de'Michieli Vitturi; Andrea Bevilacqua; Alessandro Tadini; Augusto Neri (SoftwareX, 2024)

On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband. - Luca Bellemo; Andrea Bevilacqua (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies. - Lorenzo Tomasin; Agata Iesurum; Andrea Gobbo; Andrea Neviani; Andrea Bevilacqua (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Analysis of CMRR in Doubly-Tuned Transformer Baluns. - Andrea Bevilacqua; Andrea Mazzanti (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters. - Domenico Frassetto; Stefano Cabizza; Matteo Agostinelli; Cristian Garbossa; Giorgio Spiazzi; Andrea Bevilacqua; Andrea Neviani (ICICDT, 2025)

A Driving Methodology for Four-Quadrant Power Switches Using CMOS Transistor Stacking. - Luca Bellemo; Andrea Neviani; Andrea Bevilacqua (NewCAS, 2025)