A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs. - Stefano Brenna; Andrea Bonetti; Andrea Bonfanti; Andrea L. Lacaita (MIPRO, 2014)

A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs. - Stefano Brenna; Andrea Bonetti; Andrea L. Lacaita; Andrea Bonfanti (UKSim, 2014)

A tool for the assisted design of charge redistribution SAR ADCs. - Stefano Brenna; Andrea Bonetti; Andrea Bonfanti; Andrea L. Lacaita (DATE, 2015)

An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. - Andrea Bonetti; Adam Teman; Andreas Burg 001 (ISCAS, 2015)

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder. - Pascal Andreas Meinerzhagen; Andrea Bonetti; Georgios Karakonstantis; Christoph Roth; Frank Giirkaynak; Andreas Peter Burg (ISCAS, 2015)

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters. - Stefano Brenna; Luca Bettini; Andrea Bonetti; Andrea Bonfanti; Andrea L. Lacaita (NORCAS, 2015)

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. - Jeremy Constantin; Andrea Bonetti; Adam Teman; Thomas Christoph Müller; Lorenz Schmid; Andreas Burg 001 (ESSCIRC, 2016)

An efficient tool for the assisted design of SAR ADCs capacitive DACs. - Stefano Brenna; Andrea Bonetti; Andrea Bonfanti; Andrea L. Lacaita (Integr., 2016)

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. - Pascal Giard; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Andrea Bonetti; Claude Thibeault; Warren J. Gross; Philippe Flatresse; Andreas Burg 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. - Andrea Bonetti; Adam Teman; Philippe Flatresse; Andreas Burg 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. - Andrea Bonetti; Nicholas Preyss; Adam Teman; Andreas Burg 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. - Andrea Bonetti; Jeremy Constantin; Adam Ternan; Andreas Burg 001 (ISCAS, 2018)

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. - Jonathan Narinx; Robert Giterman; Andrea Bonetti; Nicolas Frigerio; Cosimo Aprile; Andreas Burg 001; Yusuf Leblebici (A-SSCC, 2019)

FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems. - Marco Widmer; Andrea Bonetti; Andreas Burg 001 (DAC, 2019)

Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space. - Ester Vicario Bravo; Andrea Bonetti; Andreas Burg 001 (ISCAS, 2019)

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. - Robert Giterman; Andrea Bonetti; Andreas Burg 001; Adam Teman (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. - Robert Giterman; Andrea Bonetti; Andreas Burg 001; Adam Teman (ISCAS, 2020)

Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices. - Benoît W. Denkinger; Flavio Ponzina; Soumya Basu 002; Andrea Bonetti; Szabolcs Balási; Martino Ruggiero; Miguel Peón-Quirós; Davide Rossi; Andreas Burg 001; David Atienza (IEEE Des. Test, 2020)

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. - Robert Giterman; Andrea Bonetti; Ester Vicario Bravo; Tzachi Noy; Adam Teman; Andreas Burg 001 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Gain-Cell Embedded DRAMs: Modeling and Design Space. - Andrea Bonetti; Roman Golman; Robert Giterman; Adam Teman; Andreas Burg 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs. - Enric M. Calvo; Philippe Renevey; Mathieu Lemay; Andrea Bonetti; Marc Pons Solé; Régis Cattenoz; Stéphane Emery; Ricard Delgado-Gonzalo (EMBC, 2021)

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs. - Petar Jokic; Erfan Azarkhish; Andrea Bonetti; Marc Pons 001; Stéphane Emery; Luca Benini (ACM Trans. Embed. Comput. Syst., 2022)

GraCo - A Graph Composer for Integrated Circuits. - Stefan Uhlich; Andrea Bonetti; Arun Venkitaraman; Ali Momeni 002; Ryoga Matsuo; Chia-Yu Hsieh; Eisaku Ohbuchi; Lorenzo Servadei (CoRR, 2024)

Schemato - An LLM for Netlist-to-Schematic Conversion. - Ryoga Matsuo; Stefan Uhlich; Arun Venkitaraman; Andrea Bonetti; Chia-Yu Hsieh; Ali Momeni 002; Lukas Mauch; Augusto Capone; Eisaku Ohbuchi; Lorenzo Servadei (CoRR, 2024)

Locality-aware Surrogates for Gradient-based Black-box Optimization. - Ali Momeni 002; Stefan Uhlich; Arun Venkitaraman; Chia-Yu Hsieh; Andrea Bonetti; Ryoga Matsuo; Eisaku Ohbuchi; Lorenzo Servadei (CoRR, 2025)

SpiceMixer - Netlist-Level Circuit Evolution. - Stefan Uhlich; Andrea Bonetti; Arun Venkitaraman; Chia-Yu Hsieh; Mustafa Emre Gürsoy; Ryoga Matsuo; Lorenzo Servadei (CoRR, 2025)