Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. - Ashoka Visweswara Sathanur; Andrea Calimera; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (DATE, 2007)

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. - Andrea Calimera; Antonio Pullini; Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2007)

Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. - Andrea Calimera; Luca Benini; Enrico Macii (DATE, 2008)

Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. - Enrico Macii; Letícia Maria Veiras Bolzani; Andrea Calimera; Alberto Macii; Massimo Poncino (DSD, 2008)

Temperature-insensitive synthesis using multi-vt libraries. - Andrea Calimera; Enrico Macii; Massimo Poncino; R. Iris Bahar (ACM Great Lakes Symposium on VLSI, 2008)

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. - Ashoka Visweswara Sathanur; Andrea Calimera; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ISCAS, 2008)

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (ISLPED, 2008)

Thermal-Aware Design Techniques for Nanometer CMOS Circuits. - Andrea Calimera; Karthik Duraisami; Ashoka Visweswara Sathanur; Prassanna Sithambaram; R. Iris Bahar; Alberto Macii; Enrico Macii; Massimo Poncino (J. Low Power Electron., 2008)

Enabling concurrent clock and power gating in an industrial design flow. - Letícia Maria Veiras Bolzani; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (DATE, 2009)

NBTI-aware sleep transistor design for reliable power-gating. - Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2009)

Placement-aware Clustering for Integrated Clock and Power Gating. - Letícia Maria Veiras Bolzani; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (ISCAS, 2009)

NBTI-aware power gating for concurrent leakage and aging optimization. - Andrea Calimera; Enrico Macii; Massimo Poncino (ISLPED, 2009)

On-chip Thermal Modeling Based on SPICE Simulation. - Wei Liu 016; Andrea Calimera; Alberto Nannarelli; Enrico Macii; Massimo Poncino (PATMOS, 2009)

Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. - Gaurang Upasani; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (PATMOS, 2009)

Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits. - Andrea Calimera; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Post-placement temperature reduction techniques. - Wei Liu 016; Alberto Nannarelli; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2010)

An integrated thermal estimation framework for industrial embedded platforms. - Andrea Acquaviva; Andrea Calimera; Alberto Macii; Massimo Poncino; Enrico Macii; Matteo Giaconia; Claudio Parrella (ACM Great Lakes Symposium on VLSI, 2010)

Aging effects of leakage optimizations for caches. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2010)

Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. - Andrea Calimera; Enrico Macii; Massimo Poncino (ISCAS, 2010)

Dynamic indexing: concurrent leakage and aging optimization for caches. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (ISLPED, 2010)

Generating power-hungry test programs for power-aware validation of pipelined processors. - Andrea Calimera; Enrico Macii; Danilo Ravotto; Ernesto Sánchez 001; Matteo Sonza Reorda (SBCCI, 2010)

Dual-Vt assignment policies in ITD-aware synthesis. - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (Microelectron. J., 2010)

NBTI-Aware Clustered Power Gating. - Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Trans. Design Autom. Electr. Syst., 2010)

Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Partitioned cache architectures for reduced NBTI-induced aging. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (DATE, 2011)

Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. - Salvatore Rinaudo; Giuliana Gangemi; Andrea Calimera; Alberto Macii; Massimo Poncino (DATE, 2011)

Buffering of frequent accesses for reduced cache aging. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2011)

NBTI-aware data allocation strategies for scratchpad memory based embedded systems. - Cesare Ferri; Dimitra Papagiannopoulou; R. Iris Bahar; Andrea Calimera (LATW, 2011)

A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs. - Felipe Lavratti; Andrea Calimera; Letícia Maria Veiras Bolzani; Fabian Vargas 001; Enrico Macii (LATW, 2011)

An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. - Hossein Karimiyan; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (PATMOS, 2011)

Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. - Karthikeyan Lingasubramanian; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (PATMOS, 2011)

Power Efficient Variability Compensation Through Clustered Tunable Power-Gating. - Leandro Max de Lima Silva; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

IR-drop analysis of graphene-based power distribution networks. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2012)

Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. - Alessandro Sassone; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino; Richard Goldman; Vazgen Melikyan; Eduard Babayan; Salvatore Rinaudo (DATE, 2012)

NBTI effects on tree-like clock distribution networks. - Wei Liu 016; Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2012)

Energy-optimal caches with guaranteed lifetime. - Mirko Loghi; Haroon Mahmood; Andrea Calimera; Massimo Poncino; Enrico Macii (ISLPED, 2012)

On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture. - Hossein Karimiyan Alidash; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (PATMOS, 2012)

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. - Cesare Ferri; Dimitra Papagiannopoulou; R. Iris Bahar; Andrea Calimera (J. Electron. Test., 2012)

On-chip process variation-tracking through an all-digital monitoring architecture. - Hossein Karimiyan Alidash; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (IET Circuits Devices Syst., 2012)

Design Techniques and Architectures for Low-Leakage SRAMs. - Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Design Techniques for NBTI-Tolerant Power-Gating Architectures. - Andrea Calimera; Enrico Macii; Massimo Poncino (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints. - Andrea Calimera; Enrico Macii; Massimo Poncino (DAC, 2013)

A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. - Sandeep Miryala; Mehrdad Montazeri; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2013)

Delay model for reconfigurable logic gates based on graphene PN-junctions. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2013)

Exploration of different implementation styles for graphene-based reconfigurable gates. - Sandeep Miryala; Andrea Calimera; Massimo Poncino; Enrico Macii (ICICDT, 2013)

Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs. - Felipe Lavratti; Letícia Maria Veiras Bolzani; Andrea Calimera; Fabian Vargas 001; Enrico Macii (LATW, 2013)

Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino; Letícia Maria Veiras Bolzani Poehls (LATW, 2013)

Power modeling and characterization of Graphene-based logic gates. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (PATMOS, 2013)

Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs. - Alessandro Sassone; Wei Liu 016; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (Microelectron. J., 2013)

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. - Wei Liu 016; Andrea Calimera; Alberto Macii; Enrico Macii; Alberto Nannarelli; Massimo Poncino (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2014)

Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (DSD, 2014)

Modeling of Physical Defects in PN Junction Based Graphene Devices. - Sandeep Miryala; Matheus Oleiro; Letícia Maria Bolzani Pöhls; Andrea Calimera; Enrico Macii; Massimo Poncino (J. Electron. Test., 2014)

Row-based body-bias assignment for dynamic thermal clock-skew compensation. - Valerio Tenace; Sandeep Miryala; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (Microelectron. J., 2014)

Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (DAC, 2015)

Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores. - Yukai Chen; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2015)

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. - Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino; Luca Gaetano Amarù; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2015)

Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. - Roberto Giorgio Rizzo; Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2015)

An automated design flow for approximate circuits based on reduced precision redundancy. - Daniele Jahier Pagliari; Andrea Calimera; Enrico Macii; Massimo Poncino (ICCD, 2015)

Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs. - Felipe Lavratti; Letícia Maria Bolzani Poehls; Fabian Vargas 001; Andrea Calimera; Enrico Macii (VLSID, 2015)

Ultra-low power circuits using graphene p-n junctions and adiabatic computing. - Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (Microprocess. Microsystems, 2015)

Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2016)

Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (ISCAS, 2016)

Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. - Valentino Peluso; Andrea Calimera; Enrico Macii; Massimo Alioto (VLSI-SoC, 2016)

Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping. - Valentino Peluso; Roberto Giorgio Rizzo; Andrea Calimera; Enrico Macii; Massimo Alioto (VLSI-SoC (Selected Papers), 2016)

Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (VLSI-SoC, 2016)

Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (VLSI-SoC (Selected Papers), 2016)

Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling. - Roberto Giorgio Rizzo; Andrea Calimera (NGCAS, 2017)

Activation-Kernel Extraction through Machine Learning. - Valerio Tenace; Andrea Calimera (NGCAS, 2017)

On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling. - Roberto Giorgio Rizzo; Valentino Peluso; Andrea Calimera; Jun Zhou 017 (VLSI-SoC (Selected Papers), 2017)

Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS. - Roberto Giorgio Rizzo; Valentino Peluso; Andrea Calimera; Jun Zhou 017; Xin Liu 015 (VLSI-SoC, 2017)

All-digital embedded meters for on-line power estimation. - Daniele Jahier Pagliari; Valentino Peluso; Yukai Chen; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2018)

Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. - Giulia Santoro; Mario R. Casu; Valentino Peluso; Andrea Calimera; Massimo Alioto (DATE, 2018)

A compression-driven training framework for embedded deep neural networks. - Matteo Grimaldi; Federico Pugliese; Valerio Tenace; Andrea Calimera (INTESA@ESWEEK, 2018)

Scalable-effort ConvNets for multilevel classification. - Valentino Peluso; Andrea Calimera (ICCAD, 2018)

Logic-In-Memory Architecture For Min/Max Search. - Marco Vacca; Yaswanth Tavva; Anupam Chattopadhyay; Andrea Calimera (ICECS, 2018)

Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets. - Valentino Peluso; Andrea Calimera (ISCAS, 2018)

Multiplication by Inference using Classification Trees: A Case-Study Analysis. - Roberto Giorgio Rizzo; Valerio Tenace; Andrea Calimera (ISCAS, 2018)

Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. - Giulia Santoro; Mario R. Casu; Valentino Peluso; Andrea Calimera; Massimo Alioto (ISCAS, 2018)

Energy-Driven Precision Scaling for Fixed-Point ConvNets. - Valentino Peluso; Andrea Calimera (VLSI-SoC, 2018)

Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis. - Valentino Peluso; Andrea Calimera (VLSI-SoC (Selected Papers), 2018)

Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits. - Valerio Tenace; Andrea Calimera (VLSI-SoC, 2018)

Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling. - Roberto Giorgio Rizzo; Andrea Calimera; Jun Zhou 017 (Integr., 2018)

Quasi-exact logic functions through classification trees. - Valerio Tenace; Andrea Calimera (Integr., 2018)

Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. - Luca Mocerino; Valerio Tenace; Andrea Calimera (DATE, 2019)

Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms. - Valentino Peluso; Antonio Cipolletta; Andrea Calimera; Matteo Poggi; Fabio Tosi; Stefano Mattoccia (DATE, 2019)

SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. - Valerio Tenace; Roberto Giorgio Rizzo; Debjyoti Bhattacharjee; Anupam Chattopadhyay; Andrea Calimera (DATE, 2019)

CoopNet: Cooperative Convolutional Neural Network for Low-Power MCUs. - Luca Mocerino; Andrea Calimera (ICECS, 2019)

Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores. - Valentino Peluso; Antonio Cipolletta; Francesco Vaiana; Andrea Calimera (ICECS, 2019)

Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets. - Valentino Peluso; Roberto Giorgio Rizzo; Antonio Cipolletta; Andrea Calimera (SNAMS, 2019)

Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors. - Valentino Peluso; Matteo Grimaldi; Andrea Calimera (VLSI-SoC, 2019)

Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores. - Matteo Grimaldi; Valentino Peluso; Andrea Calimera (IEEE Access, 2019)

Layer-Wise Compressive Training for Convolutional Neural Networks. - Matteo Grimaldi; Valerio Tenace; Andrea Calimera (Future Internet, 2019)

EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. - Matteo Grimaldi; Valentino Peluso; Andrea Calimera (AICAS, 2020)

TentacleNet: A Pseudo-Ensemble Template for Accurate Binary Convolutional Neural Networks. - Luca Mocerino; Andrea Calimera (AICAS, 2020)

Enabling monocular depth perception at the very edge. - Valentino Peluso; Antonio Cipolletta; Andrea Calimera; Matteo Poggi; Fabio Tosi; Filippo Aleotti; Stefano Mattoccia (CVPR Workshops, 2020)

Optimization Tools for ConvNets on the Edge. - Valentino Peluso; Enrico Macii; Andrea Calimera (VLSI-SOC, 2020)

Corrigendum to"Approximate error detection-correction for efficient adaptive voltage Over-Scaling"[Integration 63 (2018) 220-231]. - Roberto Giorgio Rizzo; Andrea Calimera; Jun Zhou 017 (Integr., 2020)

Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. - Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Ultra-compact binary neural networks for human activity recognition on RISC-V processors. - Francesco Daghero; Chen Xie; Daniele Jahier Pagliari; Alessio Burrello; Marco Castellano; Luca Gandolfi; Andrea Calimera; Enrico Macii; Massimo Poncino (CF, 2021)

On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage. - Antonio Cipolletta; Andrea Calimera (DAC, 2021)

Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks. - Antonio Cipolletta; Andrea Calimera (DATE, 2021)

ACME: An Energy-Efficient Approximate Bus Encoding for I2C. - Chen Xie; Daniele Jahier Pagliari; Andrea Calimera; Enrico Macii; Massimo Poncino (ISLPED, 2021)

Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers. - Francesco Daghero; Alessio Burrello; Chen Xie; Luca Benini; Andrea Calimera; Enrico Macii; Massimo Poncino; Daniele Jahier Pagliari (VLSI-SoC, 2021)

Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers. - Francesco Daghero; Alessio Burrello; Chen Xie; Luca Benini; Andrea Calimera; Enrico Macii; Massimo Poncino; Daniele Jahier Pagliari (VLSI-SoC (Selected Papers), 2021)

AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets. - Luca Mocerino; Roberto Giorgio Rizzo; Valentino Peluso; Andrea Calimera; Enrico Macii (VLSI-SoC, 2021)

On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets. - Luca Mocerino; Roberto Giorgio Rizzo; Valentino Peluso; Andrea Calimera; Enrico Macii (VLSI-SoC (Selected Papers), 2021)

Adaptive Test-Time Augmentation for Low-Power CPU. - Luca Mocerino; Roberto Giorgio Rizzo; Valentino Peluso; Andrea Calimera; Enrico Macii (CoRR, 2021)

Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools. - Tania Cerquitelli; Daniele Jahier Pagliari; Andrea Calimera; Lorenzo Bottaccioli; Edoardo Patti; Andrea Acquaviva; Massimo Poncino (Proc. IEEE, 2021)

Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net). - Luca Mocerino; Andrea Calimera (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets. - Roberto Giorgio Rizzo; Valentino Peluso; Andrea Calimera (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs. - Chen Xie; Francesco Daghero; Yukai Chen; Marco Castellano; Luca Gandolfi; Andrea Calimera; Enrico Macii; Massimo Poncino; Daniele Jahier Pagliari (ISCAS, 2022)

SMART-IC: Smart Monitoring and Production Optimization for Zero-waste Semiconductor Manufacturing. - Khaled Sidahmed Sidahmed Alamin; Yukai Chen; Sebastiano Gaiardelli; Stefano Spellini; Andrea Calimera; Alessandro Beghi; Gian Antonio Susto; Franco Fummi; Enrico Macii; Sara Vinco (LATS, 2022)

Energy-efficient and Privacy-aware Social Distance Monitoring with Low-resolution Infrared Sensors and Adaptive Inference. - Chen Xie; Daniele Jahier Pagliari; Andrea Calimera (PRIME, 2022)

Editorial: Language and Vision in Robotics: Emerging Neural and On-Device Approaches. - Giovanni Luca Masala; Massimo Esposito; Umberto Maniscalco; Andrea Calimera (Frontiers Comput. Sci., 2022)

Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs. - Antonio Cipolletta; Valentino Peluso; Andrea Calimera; Matteo Poggi; Fabio Tosi; Filippo Aleotti; Stefano Mattoccia (IEEE Internet Things J., 2022)

Monocular Depth Perception on Microcontrollers for Edge Applications. - Valentino Peluso; Antonio Cipolletta; Andrea Calimera; Matteo Poggi; Fabio Tosi; Filippo Aleotti; Stefano Mattoccia (IEEE Trans. Circuits Syst. Video Technol., 2022)

Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks. - Francesco Daghero; Alessio Burrello; Chen Xie; Marco Castellano; Luca Gandolfi; Andrea Calimera; Enrico Macii; Massimo Poncino; Daniele Jahier Pagliari (ACM Trans. Embed. Comput. Syst., 2022)

Concurrent Pipeline Stages Optimization for Embedded Keyword Spotting. - Giacomo Zema; Valentino Peluso; Andrea Calimera; Enrico Macii (AIIoT, 2023)

Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services. - Erich Malan; Valentino Peluso; Andrea Calimera; Enrico Macii (ISLPED, 2023)

Dynamic ConvNets on Tiny Devices via Nested Sparsity. - Matteo Grimaldi; Luca Mocerino; Antonio Cipolletta; Andrea Calimera (IEEE Internet Things J., 2023)

Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference. - Chen Xie; Alessio Burrello; Francesco Daghero; Luca Benini; Andrea Calimera; Enrico Macii; Massimo Poncino; Daniele Jahier Pagliari (Sensors, 2023)

Communication-Efficient Federated Learning With Gradual Layer Freezing. - Erich Malan; Valentino Peluso; Andrea Calimera; Enrico Macii (IEEE Embed. Syst. Lett., 2023)

Efficient Deep Learning Models for Privacy-Preserving People Counting on Low-Resolution Infrared Arrays. - Chen Xie; Francesco Daghero; Yukai Chen; Marco Castellano; Luca Gandolfi; Andrea Calimera; Enrico Macii; Massimo Poncino; Daniele Jahier Pagliari (IEEE Internet Things J., 2023)

Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption. - Valentino Peluso; Erich Malan; Andrea Calimera; Enrico Macii (ICCD, 2024)

Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning. - Erich Malan; Valentino Peluso; Andrea Calimera; Enrico Macii; Paolo Montuschi (IEEE Internet Things J., 2024)

Privacy-Preserving Federated Learning for Household Characteristic Identification. - Erich Malan; Claudia De Vizia; Marco Castangia; Valentino Peluso; Andrea Calimera; Enrico Macii (COMPSAC, 2025)

Adaptive Client Participation in Budget-Constrained Federated Learning with Extreme Label Skew. - Erich Malan; Valentino Peluso; Andrea Calimera; Enrico Macii (NewCAS, 2025)