A low-power low-voltage MOSFET-only voltage reference. - Ferdinando Bedeschi; Edoardo Bonizzoni; Andrea Fantini; Claudio Resta; Guido Torelli (ISCAS (1), 2004)

High-Efficiency Regulated Charge Pump for Non-Volatile Memories. - Alessandro Cabrini; Andrea Fantini; Guido Torelli (ICECS, 2006)

Impact of control signal skews on self-boosted charge pumps. - Andrea Fantini; Alessandro Cabrini; Guido Torelli (ECCTD, 2007)

Impact of Control Signal Non-Idealties on Two-Phase Charge Pumps. - Andrea Fantini; Alessandro Cabrini; Guido Torelli (ISCAS, 2007)

Temperature dependence of the programmed states in GST-based multilevel phase-change memories. - Alessandro Cabrini; Andrea Fantini; Fabio Gallazzi; Guido Torelli (ICECS, 2008)

A Multi-Level-Cell Bipolar-Selected Phase-Change Memory. - Ferdinando Bedeschi; Rich Fackenthal; Claudio Resta; Enzo Michele Donzè; Meenatchi Jagasivamani; Egidio Cassiodoro Buda; Fabio Pellizzer; David W. Chow; Alessandro Cabrini; Giacomo Matteo Angelo Calvi; Roberto Faravelli; Andrea Fantini; et al. (ISSCC, 2008)

A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage. - Ferdinando Bedeschi; Rich Fackenthal; Claudio Resta; Enzo Michele Donzè; Meenatchi Jagasivamani; Egidio Cassiodoro Buda; Fabio Pellizzer; David W. Chow; Alessandro Cabrini; Giacomo Matteo Angelo Calvi; Roberto Faravelli; Andrea Fantini; et al. (IEEE J. Solid State Circuits, 2009)

Optimization of the write algorithm at low-current (10μA) in Cu/Al2O3-based conductive-bridge RAM. - Attilio Belmonte; Andrea Fantini; Augusto Redolfi; M. Houssa; Malgorzata Jurczak; Ludovic Goux (ESSDERC, 2015)

Engineering of a TiN Al2O3 (Hf, Al)O2 Ta2O5 Hf RRAM cell for fast operation at low current. - C. Y. Chen; Ludovic Goux; Andrea Fantini; Robin Degraeve; Augusto Redolfi; Guido Groeseneken; Malgorzata Jurczak (ESSDERC, 2015)

Experimenting an Embedded-sensor Network for Early Warning of Natural Risks Due to Fast Failures along Railways. - Andrea Fantini; Massimo Magrini; Salvatore Martino; Davide Moroni; Gabriele Pieri; Alberto Prestininzi; Ovidio Salvetti (IMTA, 2015)

Rock Falls Impacting Railway Tracks: Detection Analysis through an Artificial Intelligence Camera Prototype. - Andrea Fantini; Matteo Fiorucci; Salvatore Martino (Wirel. Commun. Mob. Comput., 2017)

Monolithically integrated 1 TFT-1RRAM non-volatile memory cells fabricated on PI flexible substrate. - Ana Lebanov; Andrea Fantini; Robin Degraeve; Manoj Nag; Myriam Willegems; Steve Smout; Soeren Steudel; Jan Genoe; Paul Heremans; Kris Myny (ESSDERC, 2018)

A Cautionary Note When Looking for a Truly Reconfigurable Resistive RAM PUF. - Kai-Hsin Chuang; Robin Degraeve; Andrea Fantini; Guido Groeseneken; Dimitri Linten; Ingrid Verbauwhede (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018)

Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications. - Jonas Doevenspeck; Robin Degraeve; Andrea Fantini; Peter Debacker; Diederik Verkest; Rudy Lauwereins; Wim Dehaene (IRPS, 2019)

Threshold switching in a-Si and a-Ge based MSM selectors and its implications for device reliability. - Taras Ravsher; Shamin H. Sharifi; Andrea Fantini; Hubert Hody; Thomas Witters; Daniele Garbin; Robin Degraeve; Valeri Afanas'ev; Jan Van Houdt; Ludovic Goux; D. Crotti; Gouri Sankar Kar (IMW, 2021)

Modeling and spectroscopy of ovonic threshold switching defects. - Robin Degraeve; Taras Ravsher; Shoichi Kabuyanagi; Andrea Fantini; Sergiu Clima; Daniele Garbin; Gouri Sankar Kar (IRPS, 2021)

Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications. - Mohit Gupta 004; Manu Perumkunnil; Andrea Fantini; Saeideh Alinezhad Chamazcoti; Woojin Kim; Marie Garcia Bardon; Gouri Sankar Kar; Arnaud Furnémont (ESSDERC, 2022)

Degradation mechanism of amorphous IGZO-based bipolar metal-semiconductor-metal selectors. - Taras Ravsher; Andrea Fantini; Adrian Vaisman Chasin; Shamin H. Sharifi; Hubert Hody; Harold Dekkers; Thomas Witters; Jan Van Houdt; Valeri Afanas'ev; Sebastien Couet; Gouri Sankar Kar (IRPS, 2022)

Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode. - Taras Ravsher; Daniele Garbin; Andrea Fantini; Robin Degraeve; Sergiu Clima; Gabriele Luca Donadio; Shreya Kundu; Hubert Hody; Wouter Devulder; Jan Van Houdt; Valeri Afanas'ev; Romain Delhougne; et al. (VLSI Technology and Circuits, 2022)

NPN Si/SiGe memory selector with non-linearity>105 and ON-current>6MA/cm2. - Gaspard Hiblot; Taras Ravsher; Roger Loo; Bhuvaneshwari Yengula Venkata Ramana; Nathali Franchina-Vergel; Andrea Fantini; Shamin Houshmand Sharifi; Nina Bazzazian; Kurt Wostyn; Loris Angelo Labbate; Sebastien Couet; Gouri Sankar Kar (ESSDERC, 2023)

Novel Cross-Point Architecture utilizing Distributed Diode Selector for Read Margin Amplification. - Taras Ravsher; Andrea Fantini; Kruti Trivedi; Nouredine Rassoul; Harold Dekkers; Attilio Belmonte; Jan Van Houdt; Valeri Afanas'ev; Kurt Wostyn; Sebastien Couet; Gouri Sankar Kar (IMW, 2024)

Comprehensive Performance and Reliability Assessment of Se-based Selector-Only Memory. - Taras Ravsher; Robin Degraeve; Daniele Garbin; Sergiu Clima; Andrea Fantini; Gabriele Luca Donadio; Shreya Kundu; Wouter Devulder; Hubert Hody; Goedele Potoms; Jan Van Houdt; Valeri Afanas'ev; et al. (IRPS, 2024)

Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology. - Koji Sakui; Daniele Garbin; Yoshihisa Iwata; Gautam Gaddemane; Yisuo Li; Yiqun Wan; Ken'ichi Kanazawa; Eyup Can Demir; Iwao Kunishima; Andrea Fantini; Masakazu Kakumu; Christophe Lorant; et al. (IMW, 2025)