Concrete Impact of Formal Verification on Quality in IP Design and Implementation. - Umberto Rossi; Andrea Fedeli; Marco Boschini; Franco Toto (ISQED, 2001)

Formal Verification Techniques: Industrial Status and Perspectives. - Joel Blasquez; Marten van Hulst; Andrea Fedeli; Jean-Luc Lambert; Dominique Borrione; Coby Hanoch; Pierre Bricaud (DATE, 2002)

An error simulation based approach to measure error coverage of formal properties. - Paolo Azzoni; Andrea Fedeli; Franco Fummi; Graziano Pravadelli; Umberto Rossi; Franco Toto (ACM Great Lakes Symposium on VLSI, 2002)

A 1000X speed up for properties completeness evaluation. - A. Castelnuovo; Andrea Fedeli; Alessandro Fin; Franco Fummi; Graziano Pravadelli; Umberto Rossi; F. Sforza; Franco Toto (HLDVT, 2002)

Modeling Flexible Real Time Systems with Preemptive Time Petri Nets. - Giacomo Bucci; Andrea Fedeli; Luigi Sassoli; Enrico Vicario (ECRTS, 2003)

Predicting Timeliness of Reactive Systems under Flexible Scheduling. - Giacomo Bucci; Andrea Fedeli; Enrico Vicario (ISADS, 2003)

On the Use of a High-Level Fault Model to Check Properties Incompleteness. - Franco Fummi; Graziano Pravadelli; Andrea Fedeli; Umberto Rossi; Franco Toto (MEMOCODE, 2003)

Specification and Simulation of Real Time Concurrent Systems Using Standard SDL Tools. - Giacomo Bucci; Andrea Fedeli; Enrico Vicario (SDL Forum, 2003)

A Verification Methodology for Reconfigurable Systems. - Michele Borgatti; Andrea Fedeli; Umberto Rossi; Jean-Luc Lambert; Imed Moussa; Franco Fummi; Cristina Marconcini; Graziano Pravadelli (MTV, 2004)

Timed State Space Analysis of Real-Time Preemptive Systems. - Giacomo Bucci; Andrea Fedeli; Luigi Sassoli; Enrico Vicario (IEEE Trans. Software Eng., 2004)

Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling. - Nicola Bombieri; Andrea Fedeli; Franco Fummi (MEMOCODE, 2005)

On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. - Nicola Bombieri; Andrea Fedeli; Franco Fummi (MTV, 2005)

SC2SCFL: Automated SystemC to SystemCFL Translation. - Ka Lok Man; Andrea Fedeli; Michele Mercaldi; Menouer Boubekeur; Michel P. Schellekens (SAMOS, 2007)

Hybrid, Incremental Assertion-Based Verification for TLM Design Flows. - Nicola Bombieri; Franco Fummi; Graziano Pravadelli; Andrea Fedeli (IEEE Des. Test Comput., 2007)

Properties Incompleteness Evaluation by Functional Verification. - Andrea Fedeli; Franco Fummi; Graziano Pravadelli (IEEE Trans. Computers, 2007)