Design Issues of LC Tuned Oscillators for Integrated Transceivers. - Carlo Samori; Andrea L. Lacaita; Alfio Zanchi; P. Vita (Great Lakes Symposium on VLSI, 1998)

Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's. - Carlo Samori; Andrea L. Lacaita; Alfio Zanchi; Salvatore Levantino; Giovanni Calí (IEEE J. Solid State Circuits, 2000)

Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO. - Alfio Zanchi; Andrea Bonfanti; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (CICC, 2001)

A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop. - Alfio Zanchi; Carlo Samori; Salvatore Levantino; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2001)

Integrated LC oscillators for frequency synthesis in wireless applications. - Carlo Samori; Salvatore Levantino; Andrea L. Lacaita (IEEE Commun. Mag., 2002)

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. - Salvatore Levantino; Carlo Samori; Andrea Bonfanti; Sander L. J. Gierkink; Andrea L. Lacaita; Vito Boccuzzi (IEEE J. Solid State Circuits, 2002)

A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application. - Andrea Giovanni Bonfanti; Salvatore Levantino; Stefano Pellerano; Carlo Samori; Andrea L. Lacaita; Felice Torrisi (ESSCIRC, 2003)

A DDS-based PLL for 2.4-GHz frequency synthesis. - Andrea Bonfanti; F. Amorosa; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Differential tuning oscillators with reduced flicker noise upconversion. - Salvatore Levantino; Andrea Bonfanti; Luca Romanò; Carlo Samori; Andrea L. Lacaita (ICECS, 2004)

A multi-tank LC-oscillator [microwave oscillator example]. - Luca Romanò; Carlo Samori; Salvatore Levantino; Andrea Bonfanti; Andrea L. Lacaita (ICECS, 2004)

Fast-switching analog PLL with finite-impulse response. - Salvatore Levantino; Luca Romanò; Carlo Samori; Andrea L. Lacaita (ISCAS (4), 2004)

Phase noise and accuracy in quadrature oscillators. - Luca Romanò; Salvatore Levantino; Andrea Bonfanti; Carlo Samori; Andrea L. Lacaita (ISCAS (1), 2004)

Phase noise in digital frequency dividers. - Salvatore Levantino; Luca Romanò; Stefano Pellerano; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2004)

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. - Stefano Pellerano; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2004)

Fast-switching analog PLL with finite-impulse response. - Salvatore Levantino; Marco Milani; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter. - Luigi Panseri; Luca Romanò; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (CICC, 2006)

5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS. - Luca Romanò; Andrea Bonfanti; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2006)

A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs. - Andrea Bonfanti; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Multiphase LC oscillators. - Luca Romanò; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Matching requirements in LINC transmitters for OFDM signals. - Luca Romanò; Luigi Panseri; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN. - Andrea Bonfanti; Carlo Samori; Andrea L. Lacaita (ESSCIRC, 2007)

An integrated low-noise multichannel system for neural signals amplification. - Tommaso Borghi; Andrea Bonfanti; Guido Zambra; Riccardo Gusmeroli; Andrea L. Lacaita; Alessandro S. Spinelli; Gytis Baranauskas (ESSCIRC, 2007)

Quantization Effects in All-Digital Phase-Locked Loops. - Paolo Madoglio; Marco Zanuso; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter. - Luigi Panseri; Luca Romanò; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2008)

An all-digital architecture for low-jitter regulated delay lines. - Salvatore Levantino; Marco Zanuso; Davide Tasca; Carlo Samori; Andrea L. Lacaita (ICECS, 2009)

A glitch-corrector circuit for low-spur ADPLLs. - Marco Zanuso; Salvatore Levantino; Davide Tasca; Daniele Raiteri; Carlo Samori; Andrea L. Lacaita (ICECS, 2009)

Noise Analysis and Minimization in Bang-Bang Digital PLLs. - Marco Zanuso; Davide Tasca; Salvatore Levantino; Andrea Donadel; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A multi-channel low-power IC for neural spike recording with data compression and narrowband 400-MHz MC-FSK wireless transmission. - Andrea Bonfanti; M. Ceravolo; Guido Zambra; Riccardo Gusmeroli; Tommaso Borghi; Alessandro S. Spinelli; Andrea L. Lacaita (ESSCIRC, 2010)

Time-to-digital converter with 3-ps resolution and digital linearization algorithm. - Marco Zanuso; Salvatore Levantino; Alberto Puggelli; Carlo Samori; Andrea L. Lacaita (ESSCIRC, 2010)

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. - Salvatore Levantino; Marco Zanuso; Carlo Samori; Andrea L. Lacaita (ISSCC, 2010)

A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. - Marco Zanuso; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (ISSCC, 2010)

AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. - Salvatore Levantino; Marco Zanuso; Paolo Madoglio; Davide Tasca; Carlo Samori; Andrea L. Lacaita (EURASIP J. Embed. Syst., 2010)

Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division. - Salvatore Levantino; Luca Collamati; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL. - Marco Zanuso; Paolo Madoglio; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Behavioral phase-noise analysis of charge-pump phase-locked loops. - Paolo Maffezzoni; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita; Dario D'Amore; Mauro Santomauro (ECCTD, 2011)

Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs. - Carlo Samori; Marco Zanuso; Salvatore Levantino; Andrea L. Lacaita (ISCAS, 2011)

A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. - Davide Tasca; Marco Zanuso; Giovanni Marzin; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (ISSCC, 2011)

A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power. - Davide Tasca; Marco Zanuso; Giovanni Marzin; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2011)

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. - Marco Zanuso; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2011)

Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. - Davide Tasca; Marco Zanuso; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power. - Giovanni Marzin; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (ISSCC, 2012)

A fast and accurate simulation method of impulse sensitivity function in oscillators. - Federico Pepe; Andrea Bonfanti; Andrea L. Lacaita (MIPRO, 2012)

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power. - Giovanni Marzin; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2012)

Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators. - Andrea Bonfanti; Federico Pepe; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Efficient Calculation of the Impulse Sensitivity Function in Oscillators. - Salvatore Levantino; Paolo Maffezzoni; Federico Pepe; Andrea Bonfanti; Carlo Samori; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technology. - Marcello Calabrese; Carmine Miccoli; Christian Monzio Compagnoni; Luca Chiavarone; Silvia Beltrami; Andrea Parisi; Sebastiano Bartolone; Andrea L. Lacaita; Alessandro S. Spinelli; Angelo Visconti (ICICDT, 2013)

Background adaptive linearization of high-speed digital-to-analog Converters. - Andrea Fenaroli; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (ISCAS, 2013)

A spur cancellation technique for MDLL-based frequency synthesizers. - Giovanni Marzin; Andrea Fenaroli; Giovanni Marucci; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (ISCAS, 2013)

Simulating phase noise induced from cyclostationary noise sources. - Federico Pepe; Andrea Bonfanti; Salvatore Levantino; Paolo Maffezzoni; Carlo Samori; Andrea L. Lacaita (ISCAS, 2013)

A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration. - Salvatore Levantino; Giovanni Marzin; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2013)

Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band. - Federico Pepe; Andrea Bonfanti; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2013)

Data regeneration and disturb immunity of T-RAM cells. - Halid Mulaosmanovic; Christian Monzio Compagnoni; Niccolo Castellani; Gianpietro Carnevale; Domenico Ventrice; Paolo Fantini; Alessandro S. Spinelli; Andrea L. Lacaita; Augusto Benvenuti (ESSDERC, 2014)

Cycling-induced threshold-voltage instabilities in nanoscale NAND flash memories: Sensitivity to the array background pattern. - Giovanni M. Paolucci; Massimo Ernesto Bertuccio; Christian Monzio Compagnoni; Silvia Beltrami; Alessandro S. Spinelli; Andrea L. Lacaita; Angelo Visconti (ESSDERC, 2014)

21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC. - Giovanni Marucci; Andrea Fenaroli; Giovanni Marzin; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (ISSCC, 2014)

2.9 A Background calibration technique to control bandwidth in digital PLLs. - Giovanni Marzin; Salvatore Levantino; Carlo Samori; Andrea L. Lacaita (ISSCC, 2014)

Analysis and optimization of a SAR ADC with attenuation capacitor. - Stefano Brenna; Andrea Bonfanti; Andrea Abba; Francesco Caponio; Andrea L. Lacaita (MIPRO, 2014)

A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs. - Stefano Brenna; Andrea Bonetti; Andrea Bonfanti; Andrea L. Lacaita (MIPRO, 2014)

A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs. - Stefano Brenna; Andrea Bonetti; Andrea L. Lacaita; Andrea Bonfanti (UKSim, 2014)

A tool for the assisted design of charge redistribution SAR ADCs. - Stefano Brenna; Andrea Bonetti; Andrea Bonfanti; Andrea L. Lacaita (DATE, 2015)

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters. - Stefano Brenna; Luca Bettini; Andrea Bonetti; Andrea Bonfanti; Andrea L. Lacaita (NORCAS, 2015)

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop. - Salvatore Levantino; Giovanni Marucci; Giovanni Marzin; Andrea Fenaroli; Carlo Samori; Andrea L. Lacaita (IEEE J. Solid State Circuits, 2015)

Bipolar-switching operated phase change memory (PCM) for improved high-temperature reliability. - Nicola Ciocchini; Mario Laudato; Andrea L. Lacaita; Daniele Ielmini; Mattia Boniardi; Enrico Varesi; Paolo Fantini (ESSDERC, 2016)

An efficient tool for the assisted design of SAR ADCs capacitive DACs. - Stefano Brenna; Andrea Bonetti; Andrea Bonfanti; Andrea L. Lacaita (Integr., 2016)

A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. - Stefano Brenna; Fabio Padovan; Andrea Neviani; Andrea Bevilacqua; Andrea Bonfanti; Andrea L. Lacaita (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL. - Tuan Minh Vo; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISCAS, 2017)

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices. - Alessandro S. Spinelli; Christian Monzio Compagnoni; Andrea L. Lacaita (Comput., 2017)

Reviewing the Evolution of the NAND Flash Technology. - Christian Monzio Compagnoni; Akira Goda; Alessandro S. Spinelli; Peter Feeley; Andrea L. Lacaita; Angelo Visconti (Proc. IEEE, 2017)

Random Dopant Fluctuation and Random Telegraph Noise in Nanowire and Macaroni MOSFETs. - Alessandro S. Spinelli; Christian Monzio Compagnoni; Andrea L. Lacaita (ESSDERC, 2018)

A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection. - Alessandro Garghetti; Andrea L. Lacaita; Salvatore Levantino (ICECS, 2018)

A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique. - Alessandro Garghetti; Andrea L. Lacaita; Salvatore Levantino (ISCAS, 2018)

Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. - Alessandro Truppi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino; Marco Ronchi; Marco Sosio (ISCAS, 2018)

A Background Calibration Technique to Control the Bandwidth of Digital PLLs. - Mario Mercandelli; Luigi Grimaldi; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2018)

Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops. - Mauro Leoncini; Andrea Bonfanti; Salvatore Levantino; Andrea L. Lacaita (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

High Scale-Factor Stability Frequency-Modulated MEMS Gyroscope: 3-Axis Sensor and Integrated Electronics Design. - Paolo Minotti; Stefano Dellea; Giorgio Mussi; Andrea Bonfanti; Stefano Facchinetti; Alessandro Tocchio; Valentina Zega; Claudia Comi; Andrea Leonardo Lacaita; Giacomo Langfelder (IEEE Trans. Ind. Electron., 2018)

A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. - Alessio Santiccioli; Mario Mercandelli; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (CICC, 2019)

Current Transport in Polysilicon-channel GAA MOSFETs: A Modeling Perspective. - Aurelio Mannara; Alessandro S. Spinelli; Andrea L. Lacaita; Christian Monzio Compagnoni (ESSDERC, 2019)

A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. - Luigi Grimaldi; Luca Bertulessi; Saleh Karman; Dmytro Cherniak; Alessandro Garghetti; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2019)

A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. - Luca Bertulessi; Saleh Karman; Dmytro Cherniak; Alessandro Garghetti; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2019)

A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. - Alessio Santiccioli; Mario Mercandelli; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2019)

A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking. - Alessandro Garghetti; Andrea L. Lacaita; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops. - Alessio Santiccioli; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Angelo Parisi; Luca Bertulessi; Dmytro Cherniak; Andrea Leonardo Lacaita; Carlo Samori; Salvatore Levantino (ISSCC, 2020)

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. - Alessio Santiccioli; Mario Mercandelli; Luca Bertulessi; Angelo Parisi; Dmytro Cherniak; Andrea Leonardo Lacaita; Carlo Samori; Salvatore Levantino (ISSCC, 2020)

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. - Alessio Santiccioli; Mario Mercandelli; Luca Bertulessi; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2020)

A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS. - Alessandro Garghetti; Andrea Leonardo Lacaita; David Seebacher; Matteo Bassi; Salvatore Levantino (CICC, 2021)

A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity. - Angelo Parisi; Mario Mercandelli; Carlo Samori; Andrea L. Lacaita (ICECS, 2021)

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Simone Mattia Dartizio; Abanob Shehata; Francesco Tesolin; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea Leonardo Lacaita; Michael Peter Kennedy; et al. (ISSCC, 2021)

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. - Alessio Santiccioli; Mario Mercandelli; Simone Mattia Dartizio; Francesco Tesolin; Saleh Karman; Abanob Shehata; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; et al. (ISSCC, 2021)

A Generalization of the Groszkowski's Result in Differential Oscillator Topologies. - Francesco Buccoleri; Andrea Bonfanti; Andrea L. Lacaita (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Andrea Bevilacqua; Luca Bertulessi; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; et al. (CICC, 2022)

A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea Leonardo Lacaita; et al. (ISSCC, 2022)

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2022)

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. - Simone Mattia Dartizio; Francesco Tesolin; Mario Mercandelli; Alessio Santiccioli; Abanob Shehata; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea L. Lacaita; Michael Peter Kennedy; et al. (IEEE J. Solid State Circuits, 2022)

Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology. - Alessandro Garghetti; Andrea L. Lacaita; David Seebacher; Matteo Bassi; Salvatore Levantino (IEEE J. Solid State Circuits, 2022)

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Angelo Parisi; Luca Bertulessi; Dmytro Cherniak; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2022)

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. - Luca Bertulessi; Dmytro Cherniak; Mario Mercandelli; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. - Gabriele Bè; Angelo Parisi; Luca Bertulessi; Luca Ricci; Lorenzo Scaletti; Mario Mercandelli; Andrea L. Lacaita; Salvatore Levantino; Carlo Samori; Andrea Bonfanti (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. - Giacomo Castoro; Simone Mattia Dartizio; Francesco Tesolin; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2023)

A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. - Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Francesco Buccoleri; Luca Lanzoni; Michele Rossoni; Dmytro Cherniak; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2023)

A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. - Luca Ricci; Lorenzo Scaletti; Gabriele Bè; Michele Rocco; Luca Bertulessi; Salvatore Levantino; Andrea L. Lacaita; Carlo Samori; Andrea Bonfanti (VLSI Technology and Circuits, 2023)

Phase Noise Analysis of Periodically ON/OFF Switched Oscillators. - Giacomo Castoro; Simone Mattia Dartizio; Andrea L. Lacaita; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2023)

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. - Francesco Tesolin; Simone Mattia Dartizio; Francesco Buccoleri; Alessio Santiccioli; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2023)

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. - Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2023)

A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector. - Simone Mattia Dartizio; Michele Rossoni; Francesco Tesolin; Giacomo Castoro; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (CICC, 2024)

A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC. - Pietro Salvi; Simone Mattia Dartizio; Michele Rossoni; Francesco Tesolin; Giacomo Castoro; Andrea L. Lacaita; Salvatore Levantino (CICC, 2024)

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM. - Michele Rossoni; Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Riccardo Dell'Orto; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2024)

10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion. - Francesco Tesolin; Simone Mattia Dartizio; Giacomo Castoro; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2024)

A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique. - Riccardo Moleri; Simone Mattia Dartizio; Michele Rossoni; Giacomo Castoro; Francesco Tesolin; Dmytro Cherniak; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (VLSI Technology and Circuits, 2024)

A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars. - Francesco Tesolin; Simone Mattia Dartizio; Giacomo Castoro; Francesco Buccoleri; Michele Rossoni; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2024)

A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA. - Gabriele Zanoletti; Gabriele Bè; Michele Rocco; Luca Ricci; Alessia Ceroni; Salvatore Levantino; Andrea Leonardo Lacaita; Luca Bertulessi; Andrea Bonfanti; Carlo Samori (CICC, 2025)

34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS. - Simone Mattia Dartizio; Giacomo Castoro; Stefano Gallucci; Michele Rossoni; Riccardo Moleri; Francesco Tesolin; Pietro Salvi; Saleh Karman; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2025)

34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning. - Stefano Gallucci; Francesco Tesolin; Pietro Salvi; Daniele Lodi Rizzini; Riccardo Moleri; Francesco Buccoleri; Michele Rossoni; Giacomo Castoro; Simone Mattia Dartizio; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2025)

A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk. - Luca Ricci; Gabriele Bè; Michele Rocco; Lorenzo Scaletti; Gabriele Zanoletti; Luca Bertulessi; Andrea L. Lacaita; Salvatore Levantino; Carlo Samori; Andrea Bonfanti (IEEE J. Solid State Circuits, 2025)

A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC. - Michele Rossoni; Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Riccardo Dell'Orto; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2025)

A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC. - Pietro Salvi; Simone Mattia Dartizio; Michele Rossoni; Francesco Tesolin; Giacomo Castoro; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2025)