Enhancing an x86_64 multi-core architecture with data-flow execution support. - Nam Ho; Andrea Mondelli; Alberto Scionti; Marco Solinas; Antoni Portero; Roberto Giorgi (Conf. Computing Frontiers, 2015)

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. - Andrea Mondelli; Nam Ho; Alberto Scionti; Marco Solinas; Antoni Portero; Roberto Giorgi (DSD, 2015)

Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters. - Pierre Michaud; Andrea Mondelli; André Seznec (ACM Trans. Archit. Code Optim., 2015)

Revisiting Wide Superscalar Microarchitecture. - Andrea Mondelli (2017)

The gem5 Simulator: Version 20.0+. - Jason Lowe-Power; Abdul Mutaal Ahmad; Ayaz Akram; Mohammad Alian; Rico Amslinger; Matteo Andreozzi; Adrià Armejach; Nils Asmussen; Srikant Bharadwaj; Gabe Black; Gedare Bloom; Bobby R. Bruce; et al. (CoRR, 2020)

SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side Channels. - Andrea Mondelli; Paul Gazzillo; Yan Solihin (DAC, 2021)

A General Framework for Accelerator Management Based on ISA Extension. - Elham Cheshmikhani; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2022)

A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives. - Biagio Peccerillo; Mirco Mannino; Andrea Mondelli; Sandro Bartolini (J. Syst. Archit., 2022)

Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (CF, 2023)

Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2023)

IXIAM: ISA EXtension for Integrated Accelerator Management. - Biagio Peccerillo; Elham Cheshmikhani; Mirco Mannino; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2023)

DeVAS: Decoupled Virtual Address Spaces. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (SBAC-PAD, 2024)

An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities. - Qijun Zhang; Mengming Li; Andrea Mondelli; Zhiyao Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)