A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology. - Andrea Pallotta; Francesco Centurelli; Francesco Loriga; Alessandro Trifiletti (Broadband European Networks and Multimedia Services, 1998)

A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. - Andrea Pallotta; Francesco Centurelli; Alessandro Trifiletti (ISLPED, 2000)

Millimeter-wave 14dBm CMOS power amplifier with input-output distributed transformers. - Andrea Pallotta; Wissam Eyssa; Luca Larcher; Riccardo Brama (CICC, 2010)

SiGe: BiCMOS technology is enabling D-band link with Active Phased Antenna Array. - Andrea Pallotta; Pascal Roux; David del Rio; Juan F. Sevillano; Mahmoud Mahdipour Pirbazari; Andrea Mazzanti; Vladimir Ermolov; Antti Lamminen; Jussi Säily; Mario G. L. Frecassetti; Maurizio Moretto; J. De Cos (EuCNC/6G Summit, 2021)

Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications. - Giandomenico Amendola; Luigi Boccia; Francesco Centurelli; Pascal Chevalier 002; Alessandro Fonte; Carmine Mustacchio; Andrea Pallotta; Pasquale Tommasino; Antonio Traversa; Alessandro Trifiletti (IEEE Trans. Circuits Syst. II Express Briefs, 2021)