Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. - Gregorio Cappuccino; Andrea Pugliese 002; Giuseppe Cocorullo (PATMOS, 2005)

A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. - Andrea Pugliese 002; Gregorio Cappuccino; Giuseppe Cocorullo (PATMOS, 2006)

Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. - Andrea Pugliese 002; Gregorio Cappuccino; Giuseppe Cocorullo (PATMOS, 2006)

Design methodology of nested-Miller amplifiers for small capacitive loads. - Andrea Pugliese 002; Gregorio Cappuccino; Giuseppe Cocorullo (ECCTD, 2007)

Settling Time Minimization of Operational Amplifiers. - Andrea Pugliese 002; Gregorio Cappuccino; Giuseppe Cocorullo (PATMOS, 2007)

Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. - Andrea Pugliese 002; Francesco A. Amoroso; Gregorio Cappuccino; Giuseppe Cocorullo (PATMOS, 2008)

Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers. - Andrea Pugliese 002; Gregorio Cappuccino; Giuseppe Cocorullo (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Design considerations for fast-settling two-stage Miller-compensated operational amplifiers. - Francesco A. Amoroso; Andrea Pugliese 002; Gregorio Cappuccino (ICECS, 2009)

Class-AB output stage design for high-speed three-stage op-amps. - Gregorio Cappuccino; Francesco A. Amoroso; Andrea Pugliese 002 (ICECS, 2009)

Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances. - Andrea Pugliese 002; Francesco A. Amoroso; Gregorio Cappuccino; Giuseppe Cocorullo (ISCAS, 2009)

Settling Time Optimization for Three-Stage CMOS Amplifier Topologies. - Andrea Pugliese 002; Francesco A. Amoroso; Gregorio Cappuccino; Giuseppe Cocorullo (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance. - Andrea Pugliese 002; Francesco A. Amoroso; Gregorio Cappuccino; Giuseppe Cocorullo (Microelectron. J., 2010)

Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances. - Andrea Pugliese 002; Francesco A. Amoroso; Gregorio Cappuccino; Giuseppe Cocorullo (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582]. - Andrea Pugliese 002; Francesco A. Amoroso; Gregorio Cappuccino; Giuseppe Cocorullo (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Design criterion for high-speed low-power SC circuits. - Francesco A. Amoroso; Andrea Pugliese 002; Gregorio Cappuccino (Int. J. Circuit Theory Appl., 2011)

Design approach for high-bandwidth low-power three-stage operational amplifiers. - Andrea Pugliese 002; Francesco A. Amoroso; Gregorio Cappuccino; Giuseppe Cocorullo (Int. J. Circuit Theory Appl., 2012)

A new efficient SC integrator scheme for high-speed low-power applications. - Francesco A. Amoroso; Andrea Pugliese 002; Gregorio Cappuccino (Int. J. Circuit Theory Appl., 2012)