Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. - Andreas Becher; Florian Bauer; Daniel Ziener; Jürgen Teich (FPL, 2014)

Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. - Robért Glein; Florian Rittner; Andreas Becher; Daniel Ziener; Jürgen Frickel; Jürgen Teich; Albert Heuberger (AHS, 2015)

A co-design approach for accelerated SQL query processing via FPGA-based data filtering. - Andreas Becher; Daniel Ziener; Klaus Meyer-Wegener; Jürgen Teich (FPT, 2015)

A LUT-Based Approximate Adder. - Andreas Becher; Jorge Echavarria; Daniel Ziener; Stefan Wildermann; Jürgen Teich (FCCM, 2016)

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. - Jorge Echavarria; Stefan Wildermann; Andreas Becher; Jürgen Teich; Daniel Ziener (FPT, 2016)

Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. - Andreas Becher; Jutta Pirkl; Achim Herrmann; Jürgen Teich; Stefan Wildermann (ReConFig, 2016)

ReOrder: Runtime datapath generation for high-throughput multi-stream processing. - Andreas Becher; Stefan Wildermann; Moritz Mühlenthaler; Jürgen Teich (ReConFig, 2016)

FPGA-Based Dynamically Reconfigurable SQL Query Processing. - Daniel Ziener; Florian Bauer; Andreas Becher; Christopher Dennl; Klaus Meyer-Wegener; Ute Schürfeld; Jürgen Teich; Jörg-Stephan Vogt; Helmut Weber (ACM Trans. Reconfigurable Technol. Syst., 2016)

Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. - Jutta Pirkl; Andreas Becher; Jorge Echavarria; Jürgen Teich; Stefan Wildermann (SCOPES, 2017)

Optimistic regular expression matching on FPGAs for near-data processing. - Andreas Becher; Stefan Wildermann; Jürgen Teich (DaMoN, 2018)

Can Approximate Computing Reduce Power Consumption on FPGAs? - Jorge Echavarria; Katja Schutz; Andreas Becher; Stefan Wildermann; Jürgen Teich (ICECS, 2018)

Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. - Franz-Josef Streit; Martín Letras; Stefan Wildermann; Benjamin Hackenberg; Joachim Falk; Andreas Becher; Jürgen Teich (ReConFig, 2018)

Integration of FPGAs in Database Management Systems: Challenges and Opportunities. - Andreas Becher; Lekshmi B. G.; David Broneske; Tobias Drewes; Bala Gurumurthy; Klaus Meyer-Wegener; Thilo Pionteck; Gunter Saake; Jürgen Teich; Stefan Wildermann (Datenbank-Spektrum, 2018)

ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. - Andreas Becher; Achim Herrmann; Stefan Wildermann; Jürgen Teich (BTW (Workshops), 2019)

In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. - Andreas Becher; Jürgen Teich (DaMoN, 2019)

Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. - Patrick Plagwitz; Franz-Josef Streit; Andreas Becher; Stefan Wildermann; Jürgen Teich (ReConFig, 2019)

The ReProVide query-sequence optimization in a hardware-accelerated DBMS. - Lekshmi Beena Gopalakrishnan Nair; Andreas Becher; Klaus Meyer-Wegener (DaMoN, 2020)

SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. - Lekshmi B. G.; Andreas Becher; Klaus Meyer-Wegener; Stefan Wildermann; Jürgen Teich (EDBT, 2020)

Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. - Franz-Josef Streit; Florian Fritz; Andreas Becher; Stefan Wildermann; Stefan Werner; Martin Schmidt-Korth; Michael Pschyklenk; Jürgen Teich (HOST, 2020)

Query-Sequence Optimization on a Reconfigurable Hardware-Accelerated System. - Lekshmi B. G.; Andreas Becher; Klaus Meyer-Wegener (CoRR, 2020)

The ReProVide Query-Sequence Optimization in a Hardware-Accelerated DBMS. - Lekshmi B. G.; Andreas Becher; Klaus Meyer-Wegener (CoRR, 2020)

Choice - A Tunable PUF-Design for FPGAs. - Franz-Josef Streit; Paul Krüger; Andreas Becher; Jens Schlumberger; Stefan Wildermann; Jürgen Teich (FPL, 2021)

On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. - Jorge Echavarria; Stefan Wildermann; Oliver Keszöcze; Faramarz Khosravi; Andreas Becher; Jürgen Teich (CoRR, 2021)

Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. - Lekshmi Beena Gopalakrishnan Nair; Andreas Becher; Stefan Wildermann; Klaus Meyer-Wegener; Jürgen Teich (Datenbank-Spektrum, 2021)

Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. - Ali Asghar; Amanda Katherine Robillard; Ilya Tuzov; Andreas Becher; Daniel Ziener (ARCS, 2022)

Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. - Jens Trautmann 001; Nikolaos Patsiatzis; Andreas Becher; Stefan Wildermann; Jürgen Teich (ASHES@CCS, 2022)

Raw Filtering of JSON Data on FPGAs. - Tobias Hahn; Andreas Becher; Stefan Wildermann; Jürgen Teich (DATE, 2022)

Real-Time Waveform Matching with a Digitizer at 10 GS/s. - Jens Trautmann 001; Nikolaos Patsiatzis; Andreas Becher; Jürgen Teich; Stefan Wildermann (FPL, 2022)

Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. - Jorge Echavarria; Stefan Wildermann; Oliver Keszöcze; Faramarz Khosravi; Andreas Becher; Jürgen Teich (it Inf. Technol., 2022)

Design and Evaluation of a Tunable PUF Architecture for FPGAs. - Franz-Josef Streit; Paul Krüger; Andreas Becher; Stefan Wildermann; Jürgen Teich (ACM Trans. Reconfigurable Technol. Syst., 2022)

Near-Data Query Processing on Heterogeneous FPGA-based Systems. - Andreas Becher (2022)

Short Paper: Analysis of Vivado implementation strategies regarding side-channel leakage for FPGA-based AES implementations. - Ali Asghar; Andreas Becher; Daniel Ziener (HASP@MICRO, 2024)

Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. - Jens Trautmann 001; Paul Krüger; Andreas Becher; Stefan Wildermann; Jürgen Teich (ACM Trans. Reconfigurable Technol. Syst., 2024)