Fast parallel implementation of DFT using configurable devices. - Andreas Dandalis; Viktor K. Prasanna (FPL, 1997)

Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures. - Andreas Dandalis; Viktor K. Prasanna (FCCM, 1998)

Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures. - Andreas Dandalis; Viktor K. Prasanna (FPL, 1998)

Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices. - Andreas Dandalis; Alessandro Mei; Viktor K. Prasanna (IPPS/SPDP Workshops, 1999)

A Comparative Study of Performance of AES Final Candidates Using FPGAs. - Andreas Dandalis; Viktor K. Prasanna; José D. P. Rolim (CHES, 2000)

An Adaptive Cryptographic Engine for IPSec Architectures. - Andreas Dandalis; Viktor K. Prasanna; José D. P. Rolim (FCCM, 2000)

A Parallel Pipelined SAT Solver for FPGAs. - Mark Redekopp; Andreas Dandalis (FPL, 2000)

Efficient Self-Reconfigurable Implementations Using On-chip Memory. - Sameer Wadhwa; Andreas Dandalis (FPL, 2000)

Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. - Andreas Dandalis; Viktor K. Prasanna; Bharani Thiruvengadam (FPL, 2001)

Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. - Andreas Dandalis; Viktor K. Prasanna (ACM Trans. Design Autom. Electr. Syst., 2002)

An adaptive cryptographic engine for internet protocol security architectures. - Andreas Dandalis; Viktor K. Prasanna (ACM Trans. Design Autom. Electr. Syst., 2004)

Configuration compression for FPGA-based embedded systems. - Andreas Dandalis; Viktor K. Prasanna (IEEE Trans. Very Large Scale Integr. Syst., 2005)