A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikolaos S. Voros (IPDPS Workshops, 2014)

FPGA Implementations for Volterra DFEs. - Andreas Emeretlis; George Theodoridis (Panhellenic Conference on Informatics, 2014)

High-performance FPGA implementations of volterra DFEs for optical fiber systems. - Andreas Emeretlis; George Theodoridis; George-Othon Glentis (ReConFig, 2014)

FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links. - Andreas Emeretlis; V. Kefelouras; George Theodoridis; Maki Nanou; Christina Tanya Politi; Kristina Georgoulakis; George-Othon Glentis (EUSIPCO, 2015)

40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links. - Maki Nanou; Andreas Emeretlis; Christina Tanya Politi; George Theodoridis; Kristina Georgoulakis; George-Othon Glentis (ICTON, 2015)

Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikos S. Voros (ISVLSI, 2015)

A hybrid approach for mapping and scheduling on heterogeneous multicore systems. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikolaos S. Voros (SAMOS, 2016)

A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikolaos S. Voros (ACM Trans. Embed. Comput. Syst., 2016)

Task graph mapping and scheduling on heterogeneous architectures under communication constraints. - Andreas Emeretlis; T. Tsakoulis; George Theodoridis; Panayiotis Alefragis; Nikos S. Voros (SAMOS, 2017)

Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikos S. Voros (ACM Trans. Design Autom. Electr. Syst., 2018)

A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikos S. Voros (VLSI-SoC, 2022)