A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. - Andreas Floros 003; Yiorgos Tsiatouhas; Angela Arapoyanni; Themistoklis Haniotakis (ICECS, 2006)

Timing Error Detection and Correction by Time Dilation. - Andreas Floros 003; Yiorgos Tsiatouhas; Xrysovalantis Kavousianos (VLSI-SoC (Selected Papers), 2008)

The Time Dilation Technique for Timing Error Tolerance. - Stefanos Valadimas; Andreas Floros 003; Yiorgos Tsiatouhas; Angela Arapoyanni; Xrysovalantis Kavousianos (IEEE Trans. Computers, 2014)