Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. - Lefteris M. Kirousis; Andreas G. Veneris (Acta Informatica, 1995)

A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. - Andreas G. Veneris; Ibrahim N. Hajj (Great Lakes Symposium on VLSI, 1997)

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits - Andreas G. Veneris (1998)

A hybrid approach to design error detection and correction [VLSI digital circuits]. - Andreas G. Veneris; Ibrahim N. Hajj (ICECS, 1999)

Correcting multiple design errors in digital VLSI circuits. - Andreas G. Veneris; Ibrahim N. Hajj (ISCAS (1), 1999)

Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. - Andreas G. Veneris; Ibrahim N. Hajj; Srikanth Venkataraman; W. Kent Fuchs (VTS, 1999)

Design error diagnosis and correction via test vector simulation. - Andreas G. Veneris; Ibrahim N. Hajj (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Design Optimization Based on Diagnosis Techniques. - Andreas G. Veneris; Magdy S. Abadir; Ibrahim N. Haji (LATW, 2000)

Design rewiring based on diagnosis techniques. - Andreas G. Veneris; Magdy S. Abadir; Ivor Ting (ASP-DAC, 2001)

ATPG Driven Logic Synthesis for Delay and Power Minimization. - Ivor Ting; Andreas G. Veneris; Magdy S. Abadir (LATW, 2001)

Incremental Diagnosis and Correction of Multiple Faults and Errors. - Andreas G. Veneris; Jiang Brandon Liu; Mandana Amiri; Magdy S. Abadir (DATE, 2002)

Design rewiring for power minimization [logic design]. - Mandana Amiri; Andreas G. Veneris; Ivor Ting (ISCAS (4), 2002)

Incremental Diagnosis of Multiple Open-Interconnects. - Jiang Brandon Liu; Andreas G. Veneris; Hiroshi Takahashi (ITC, 2002)

Design Rewiring Using ATPG. - Andreas G. Veneris; Magdy S. Abadir; Mandana Amiri (ITC, 2002)

Efficient and Exact Diagnosis of Multiple Stuck-At Faults. - Jiang Brandon Liu; Andreas G. Veneris; Magdy S. Abadir (LATW, 2002)

Design rewiring using ATPG. - Andreas G. Veneris; Magdy S. Abadir (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Logic verification based on diagnosis techniques. - Andreas G. Veneris; Alexander Smith 001; Magdy S. Abadir (ASP-DAC, 2003)

Extraction Error Diagnosis and Correction in High-Performance Designs. - Yu-Shen Yang; Jiang Brandon Liu; Paul J. Thadikaran; Andreas G. Veneris (ITC, 2003)

Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. - Andreas G. Veneris (MTV, 2003)

Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. - Yu-Shen Yang; Jiang Brandon Liu; Paul J. Thadikaran; Andreas G. Veneris (MTV, 2003)

Design diagnosis using Boolean satisfiability. - Alexander Smith 001; Andreas G. Veneris; Anastasios Viglas (ASP-DAC, 2004)

Managing Don't Cares in Boolean Satisfiability. - Sean Safarpour; Andreas G. Veneris; Rolf Drechsler; Joanne Lee (DATE, 2004)

Debugging sequential circuits using Boolean satisfiability. - Moayad Fahim Ali; Andreas G. Veneris; Alexander Smith 001; Sean Safarpour; Rolf Drechsler; Magdy S. Abadir (ICCAD, 2004)

Fault equivalence and diagnostic test generation using ATPG. - Andreas G. Veneris; Robert Chang; Magdy S. Abadir; Mandana Amiri (ISCAS (5), 2004)

Logic Rewiring for Delay and Power Minimization. - Andreas G. Veneris (J. Inf. Sci. Eng., 2004)

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. - Yu-Shen Yang; Andreas G. Veneris; Paul J. Thadikaran; Srikanth Venkataraman (DATE, 2005)

Diagnosing multiple transition faults in the absence of timing information. - Jiang Brandon Liu; Magdy S. Abadir; Andreas G. Veneris; Sean Safarpour (ACM Great Lakes Symposium on VLSI, 2005)

Utilizing don't care states in SAT-based bounded sequential problems. - Sean Safarpour; Görschwin Fey; Andreas G. Veneris; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2005)

Post-verification debugging of hierarchical designs. - Moayad Fahim Ali; Sean Safarpour; Andreas G. Veneris; Magdy S. Abadir; Rolf Drechsler (ICCAD, 2005)

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. - Andreas G. Veneris; Robert Chang; Magdy S. Abadir; Sep Seyedi (J. Electron. Test., 2005)

Incremental Design Debugging in a Logic Synthesis Environment. - Andreas G. Veneris; Jiang Brandon Liu (J. Electron. Test., 2005)

Incremental fault diagnosis. - Jiang Brandon Liu; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Fault diagnosis and logic debugging using Boolean satisfiability. - Alexander Smith 001; Andreas G. Veneris; Moayad Fahim Ali; Anastasios Viglas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Efficient SAT-based Boolean matching for FPGA technology mapping. - Sean Safarpour; Andreas G. Veneris; Gregg Baeckler; Richard Yuan (DAC, 2006)

On the relation between simulation-based and SAT-based diagnosis. - Görschwin Fey; Sean Safarpour; Andreas G. Veneris; Rolf Drechsler (DATE, 2006)

Integrating observability don't cares in all-solution SAT solvers. - Sean Safarpour; Andreas G. Veneris; Rolf Drechsler (ISCAS, 2006)

Seamless Integration of SER in Rewiring-Based Design Space Exploration. - Sobeeh Almukhaizim; Yiorgos Makris; Yu-Shen Yang; Andreas G. Veneris (ITC, 2006)

Abstraction and Refinement Techniques in Automated Design Debugging. - Sean Safarpour; Andreas G. Veneris (MTV, 2006)

Session Abstract. - Andreas G. Veneris; Yiorgos Makris (VTS, 2006)

Extraction error modeling and automated model debugging in high-performance custom designs. - Yu-Shen Yang; Andreas G. Veneris; Paul J. Thadikaran; Srikanth Venkataraman (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Trace Compaction using SAT-based Reachability Analysis. - Sean Safarpour; Andreas G. Veneris; Hratch Mangassarian (ASP-DAC, 2007)

Automating Logic Rectification by Approximate SPFDs. - Yu-Shen Yang; Subarnarekha Sinha; Andreas G. Veneris; Robert K. Brayton (ASP-DAC, 2007)

Maximum circuit activity estimation using pseudo-boolean satisfiability. - Hratch Mangassarian; Andreas G. Veneris; Sean Safarpour; Farid N. Najm; Magdy S. Abadir (DATE, 2007)

Improved Design Debugging Using Maximum Satisfiability. - Sean Safarpour; Hratch Mangassarian; Andreas G. Veneris; Mark H. Liffiton; Karem A. Sakallah (FMCAD, 2007)

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. - Hratch Mangassarian; Andreas G. Veneris; Sean Safarpour; Marco Benedetti; Duncan Exon Smith (ICCAD, 2007)

On the latency, energy and area of checkpointed, superscalar register alias tables. - Elham Safi; Patrick Akl; Andreas Moshovos; Andreas G. Veneris; Aggeliki Arapoyanni (ISLPED, 2007)

A succinct memory model for automated design debugging. - Brian Keng; Hratch Mangassarian; Andreas G. Veneris (ICCAD, 2008)

On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. - Sobeeh Almukhaizim; Yiorgos Makris; Yu-Shen Yang; Andreas G. Veneris (IOLTS, 2008)

A physical level study and optimization of CAM-based checkpointed register alias table. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (ISLPED, 2008)

Improved SAT-based Reachability Analysis with Observability Don't Cares. - Sean Safarpour; Andreas G. Veneris; Rolf Drechsler (J. Satisf. Boolean Model. Comput., 2008)

L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (IEEE Trans. Very Large Scale Integr. Syst., 2008)

The day Sherlock Holmes decided to do EDA. - Andreas G. Veneris; Sean Safarpour (DAC, 2009)

Automated data analysis solutions to silicon debug. - Yu-Shen Yang; Nicola Nicolici; Andreas G. Veneris (DATE, 2009)

Sequential logic rectifications with approximate SPFDs. - Yu-Shen Yang; Subarna Sinha; Andreas G. Veneris; Robert K. Brayton; Duncan Exon Smith (DATE, 2009)

Scaling VLSI design debugging with interpolation. - Brian Keng; Andreas G. Veneris (FMCAD, 2009)

Spatial and temporal design debug using partial MaxSAT. - Yibin Chen; Sean Safarpour; Andreas G. Veneris; João Marques-Silva 001 (ACM Great Lakes Symposium on VLSI, 2009)

Automated debugging with high level abstraction and refinement. - Sean Safarpour; Andreas G. Veneris (HLDVT, 2009)

A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (ICSAMOS, 2009)

Automated Design Debugging With Abstraction and Refinement. - Sean Safarpour; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Managing verification error traces with bounded model debugging. - Sean Safarpour; Andreas G. Veneris; Farid N. Najm (ASP-DAC, 2010)

Leveraging dominators for preprocessing QBF. - Hratch Mangassarian; Bao Le; Alexandra Goultiaeva; Andreas G. Veneris; Fahiem Bacchus (DATE, 2010)

Automated silicon debug data analysis techniques for a hardware data acquisition environment. - Yu-Shen Yang; Brian Keng; Nicola Nicolici; Andreas G. Veneris; Sean Safarpour (ISQED, 2010)

An Automated Framework for Correction and Debug of PSL Assertions. - Brian Keng; Andreas G. Veneris; Sean Safarpour (MTV, 2010)

Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. - Hratch Mangassarian; Andreas G. Veneris; Marco Benedetti (IEEE Trans. Computers, 2010)

Automated Design Debugging With Maximum Satisfiability. - Yibin Chen; Sean Safarpour; João Marques-Silva 001; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Bounded Model Debugging. - Brian Keng; Sean Safarpour; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Managing complexity in design debugging with sequential abstraction and refinement. - Brian Keng; Andreas G. Veneris (ASP-DAC, 2011)

From RTL to silicon: The case for automated debug. - Andreas G. Veneris; Brian Keng; Sean Safarpour (ASP-DAC, 2011)

Automated debugging of SystemVerilog assertions. - Brian Keng; Sean Safarpour; Andreas G. Veneris (DATE, 2011)

Sequence pair based voltage island floorplanning. - Dipanjan Sengupta; Andreas G. Veneris; Steven J. E. Wilton; André Ivanov; Res Saleh (IGCC, 2011)

Debugging with dominance: On-the-fly RTL debug solution implications. - Hratch Mangassarian; Andreas G. Veneris; Duncan Exon Smith; Sean Safarpour (ICCAD, 2011)

Automating Logic Transformations With Approximate SPFDs. - Yu-Shen Yang; Subarna Sinha; Andreas G. Veneris; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Two-Stage, Pipelined Register Renaming. - Elham Safi; Andreas Moshovos; Andreas G. Veneris (IEEE Trans. Very Large Scale Integr. Syst., 2011)

On error tolerance and Engineering Change with Partially Programmable Circuits. - Hratch Mangassarian; Hiroaki Yoshida; Andreas G. Veneris; Shigeru Yamashita; Masahiro Fujita (ASP-DAC, 2012)

Automated data analysis techniques for a modern silicon debug environment. - Yu-Shen Yang; Andreas G. Veneris; Nicola Nicolici; Masahiro Fujita (ASP-DAC, 2012)

Non-solution implications using reverse domination in a modern SAT-based debugging environment. - Bao Le; Hratch Mangassarian; Brian Keng; Andreas G. Veneris (DATE, 2012)

Leveraging reconfigurability to raise productivity in FPGA functional debug. - Zissis Poulos; Yu-Shen Yang; Jason Helge Anderson; Andreas G. Veneris; Bao Le (DATE, 2012)

Automated debugging of missing input constraints in a formal verification environment. - Brian Keng; Andreas G. Veneris (FMCAD, 2012)

Lazy suspect-set computation: fault diagnosis for deep electrical bugs. - Dipanjan Sengupta; Flavio M. de Paula; Alan J. Hu; Andreas G. Veneris; André Ivanov (ACM Great Lakes Symposium on VLSI, 2012)

Multi-objective voltage island floorplanning using sequence pair representation. - Dipanjan Sengupta; Andreas G. Veneris; Steven J. E. Wilton; André Ivanov (Sustain. Comput. Informatics Syst., 2012)

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. - Hratch Mangassarian; Andreas G. Veneris; Farid N. Najm (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. - Yu-Shen Yang; Andreas G. Veneris; Nicola Nicolici (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Reviving erroneous stability-based clock-gating using partial Max-SAT. - Bao Le; Dipanjan Sengupta; Andreas G. Veneris (ASP-DAC, 2013)

Accelerating post silicon debug of deep electrical faults. - Bao Le; Dipanjan Sengupta; Andreas G. Veneris; Zissis Poulos (IOLTS, 2013)

A failure triage engine based on error trace signature extraction. - Zissis Poulos; Yu-Shen Yang; Andreas G. Veneris (IOLTS, 2013)

Early detection of current hot spots in power gated designs. - Dipanjan Sengupta; Erhan Ergin; Andreas G. Veneris (ISLPED, 2013)

Path-Directed Abstraction and Refinement for SAT-Based Design Debugging. - Brian Keng; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Automated debugging of missing assumptions. - Brian Keng; Evean Qin; Andreas G. Veneris; Bao Le (ASP-DAC, 2014)

Multiple clock domain synchronization in a QBF-based verification environment. - Djordje Maksimovic; Bao Le; Andreas G. Veneris (ICCAD, 2014)

Simulation and satisfiability guided counter-example triage for RTL design debugging. - Zissis Poulos; Yu-Shen Yang; Andreas G. Veneris; Bao Le (ISQED, 2014)

Clustering-based failure triage for RTL regression debugging. - Zissis Poulos; Andreas G. Veneris (ITC, 2014)

Debugging RTL Using Structural Dominance. - Hratch Mangassarian; Bao Le; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Automated rectification methodologies to functional state-space unreachability. - Ryan Berryhill; Andreas G. Veneris (DATE, 2015)

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. - Andrew Becker; Djordje Maksimovic; David Novo; Mohsen Ewaida; Andreas G. Veneris; Barbara Jobstmann; Paolo Ienne (Haifa Verification Conference, 2015)

Clustering-based revision debug in regression verification. - Djordje Maksimovic; Andreas G. Veneris; Zissis Poulos (ICCD, 2015)

Mining simulation metrics for failure triage in regression testing. - Zissis Poulos; Andreas G. Veneris (IOLTS, 2015)

Constructing stability-based clock gating with hierarchical clustering. - Bao Le; Djordje Maksimovic; Dipanjan Sengupta; Erhan Ergin; Ryan Berryhill; Andreas G. Veneris (PATMOS, 2015)

A complete approach to unreachable state diagnosability via property directed reachability. - Ryan Berryhill; Andreas G. Veneris (ASP-DAC, 2016)

Root-cause analysis for memory-locked errors. - John Adler; Djordje Maksimovic; Andreas G. Veneris (DATE, 2016)

Efficient Selection of Suspect Sets in Unreachable State Diagnosis. - Ryan Berryhill; Andreas G. Veneris (ISAIM, 2016)

Revision debug with non-linear version history in regression verification. - John Adler; Ryan Berryhill; Andreas G. Veneris (IVSW, 2016)

On simulation-based metrics that characterize the behavior of RTL errors. - Zissis Poulos; Ryan Berryhill; John Adler; Andreas G. Veneris (SummerSim, 2016)

Exemplar-based Failure Triage for Regression Design Debugging. - Zissis Poulos; Andreas G. Veneris (J. Electron. Test., 2016)

An extensible perceptron framework for revision RTL debug automation. - John Adler; Ryan Berryhill; Andreas G. Veneris (ASP-DAC, 2017)

Learning support sets in IC3 and Quip: The good, the bad, and the ugly. - Ryan Berryhill; Alexander Ivrii; Neil Veira; Andreas G. Veneris (FMCAD, 2017)

Fast GPU-Based Influence Maximization Within Finite Deadlines via Node-Level Parallelism. - Koushik Pal; Zissis Poulos; Edward Kim; Andreas G. Veneris (ICDM, 2017)

Learning lemma support graphs in Quip and IC3. - Ryan Berryhill; Neil Veira; Andreas G. Veneris; Zissis Poulos (IVSW, 2017)

Leveraging Software Configuration Management in Automated RTL Design Debug. - John Adler; Andreas G. Veneris (IEEE Des. Test, 2017)

Suspect set prediction in RTL bug hunting. - Neil Veira; Zissis Poulos; Andreas G. Veneris (DATE, 2018)

Astraea: A Decentralized Blockchain Oracle. - John Adler; Ryan Berryhill; Andreas G. Veneris; Zissis Poulos; Neil Veira; Anastasia Kastania (iThings/GreenCom/CPSCom/SmartData, 2018)

Finding All Minimal Safe Inductive Sets. - Ryan Berryhill; Alexander Ivrii; Andreas G. Veneris (SAT, 2018)

Efficient suspect selection in unreachable state diagnosis. - Ryan Berryhill; Andreas G. Veneris (Ann. Math. Artif. Intell., 2018)

Methodologies for Diagnosis of Unreachable States via Property Directed Reachability. - Ryan Berryhill; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Failure Triage in RTL Regression Verification. - Zissis Poulos; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Suspect2vec: a suspect prediction model for directed RTL debugging. - Neil Veira; Zissis Poulos; Andreas G. Veneris (ASP-DAC, 2019)

Chasing Minimal Inductive Validity Cores in Hardware Model Checking. - Ryan Berryhill; Andreas G. Veneris (FMCAD, 2019)

On Public Decentralized Ledger Oracles via a Paired-Question Protocol. - Marco Merlini; Neil Veira; Ryan Berryhill; Andreas G. Veneris (IEEE ICBC, 2019)

Unsupervised Embedding Enhancements of Knowledge Graphs using Textual Associations. - Neil Veira; Brian Keng; Kanchana Padmanabhan; Andreas G. Veneris (IJCAI, 2019)

Special Drawing Rights in a New Decentralized Century. - Andreas G. Veneris; Andreas G. Park (CoRR, 2019)

A Truth-Inducing Sybil Resistant Decentralized Blockchain Oracle. - Yuxi Cai; Georgios Fragkos; Eirini-Eleni Tsiropoulou; Andreas G. Veneris (BRAINS, 2020)

Engineering Economics in the Conflux Network. - Yuxi Cai; Fan Long; Andreas G. Park; Andreas G. Veneris (BRAINS, 2020)

Verified Development and Deployment of Multiple Interacting Smart Contracts with VeriSolid. - Keerthi Nelaturu; Anastasia Mavridou; Andreas G. Veneris; Aron Laszka (IEEE ICBC, 2020)

Searching for Bugs Using Probabilistic Suspect Implications. - Neil Veira; Zissis Poulos; Andreas G. Veneris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

On Public Crowdsource-Based Mechanisms for a Decentralized Blockchain Oracle. - Keerthi Nelaturu; John Adler; Marco Merlini; Ryan Berryhill; Neil Veira; Zissis Poulos; Andreas G. Veneris (IEEE Trans. Engineering Management, 2020)

Blockchain for V2X: A Taxonomy of Design Use Cases and System Requirements. - James Meijers; Edward Au; Yuxi Cai; Hans-Arno Jacobsen; Shashank Motepalli; Robert Sun; Andreas G. Veneris; Gengrui Zhang; Shiquan Zhang (BRAINS, 2021)

Smart Contracts Refinement for Gas Optimization. - Keerthi Nelaturu; Sidi Mohamed Beillahi; Fan Long; Andreas G. Veneris (BRAINS, 2021)

Cost-Effective Blockchain-based IoT Data Marketplaces with a Credit Invariant. - James Meijers; Guntur Dharma Putra; Grammateia Kotsialou; Salil S. Kanhere; Andreas G. Veneris (IEEE ICBC, 2021)

SigVM: Toward Fully Autonomous Smart Contracts. - Ryan Song; Zihan Zhao; Yuxi Cai; Andreas G. Veneris; Fan Long (CoRR, 2021)

Automated Auditing of Price Gouging TOD Vulnerabilities in Smart Contracts. - Sidi Mohamed Beillahi; Eric Keilty; Keerthi Nelaturu; Andreas G. Veneris; Fan Long (ICBC, 2022)

LMPTs: Eliminating Storage Bottlenecks for Processing Blockchain Transactions. - Jemin Andrew Choi; Sidi Mohamed Beillahi; Peilun Li; Andreas G. Veneris; Fan Long (ICBC, 2022)

Truthful Decentralized Blockchain Oracles. - Yuxi Cai; Nafis Irtija; Eirini-Eleni Tsiropoulou; Andreas G. Veneris (Int. J. Netw. Manag., 2022)

SigVM: enabling event-driven execution for truly decentralized smart contracts. - Zihan Zhao; Sidi Mohamed Beillahi; Ryan Song; Yuxi Cai; Andreas G. Veneris; Fan Long (Proc. ACM Program. Lang., 2022)

Privacy and Transparency in CBDCs: A Regulation-by-Design AML/CFT Scheme. - Nadia Pocher; Andreas G. Veneris (IEEE Trans. Netw. Serv. Manag., 2022)

Guest Editorial: Special Issue on Recent Advances on Blockchain for Network and Service Management. - Salil S. Kanhere; Andreas G. Veneris; Sachiko Yoshihama; Sandip Chakraborty 001; Ori Rottenstreich; Marta Beltrán Pardo; Bruno Rodriguez (IEEE Trans. Netw. Serv. Manag., 2022)

Gas Optimization Patterns in Move Smart Contracts on the Aptos Blockchain. - Eric Keilty; Keerthi Nelaturu; Anastasia Kastania; Andreas G. Veneris (BRAINS, 2023)

A Robust Front-Running Methodology for Malicious Flash- Loan DeFi Attacks. - Xun Deng; Zihan Zhao; Sidi Mohamed Beillahi; Han Du; Cyrus Minwalla; Keerthi Nelaturu; Andreas G. Veneris; Fan Long (DAPPS, 2023)

Möbius: an Atomic State Sharding Design for Account-Based Blockchains. - Srisht Fateh Singh; Panagiotis Michalopoulos; Sidi Mohamed Beillahi; Andreas G. Veneris; Fan Long (ICBC, 2023)

DEEPER: Enhancing Liquidity in Concentrated Liquidity AMM DEX via Sharing. - Srisht Fateh Singh; Panagiotis Michalopoulos; Andreas G. Veneris (ICBC, 2023)

Inducing Trust in Blockchain-enabled IoT Marketplaces Through Reputation and Dispute Resolution. - Panagiotis Michalopoulos; Srisht Fateh Singh; Andreas G. Veneris (MetaCom, 2023)

Natural Language-Based Model-Checking Framework for Move Smart Contracts. - Keerthi Nelaturu; Eric Keilty; Andreas G. Veneris (SDS, 2023)

Correct-by-Design Interacting Smart Contracts and a Systematic Approach for Verifying ERC20 and ERC721 Contracts With VeriSolid. - Keerthi Nelaturu; Anastasia Mavridou; Emmanouela Stachtiari; Andreas G. Veneris; Aron Laszka (IEEE Trans. Dependable Secur. Comput., 2023)

On Tokenizing Securities in Contemporary Decentralized Finance Ecosystems. - Reina Ke Xin Li; Srisht Fateh Singh; Andreas G. Park; Andreas G. Veneris (BRAINS, 2024)

Compliance Design Options for Offline CBDCs: Balancing Privacy and AML/CFT. - Panagiotis Michalopoulos; Odunayo Olowookere; Nadia Pocher; Johannes Sedlmeir; Andreas G. Veneris; Poonam Puri (ICBC, 2024)

Option Contracts in the DeFi Ecosystem: Motivation, Solutions, & Technical Challenges. - Srisht Fateh Singh; Panagiotis Michalopoulos; Andreas G. Veneris (ICBC, 2024)

BakUP: Automated, Flexible, and Capital-Efficient Insurance Protocol for Decentralized Finance. - Srisht Fateh Singh; Panagiotis Michalopoulos; Andreas G. Veneris (ICBC, 2024)

Safeguarding DeFi Smart Contracts against Oracle Deviations. - Xun Deng; Sidi Mohamed Beillahi; Cyrus Minwalla; Han Du; Andreas G. Veneris; Fan Long (ICSE, 2024)

Innovations in Blockchain for Crypto Assets and Exchanges. - James Won-Ki Hong; Andreas G. Veneris; Hongtaek Ju 001; Taeyeol Jeong; Changhoon Kang (Int. J. Netw. Manag., 2024)

Deeper: A shared liquidity decentralized exchange design for low trading volume tokens to enhance average liquidity. - Srisht Fateh Singh; Panagiotis Michalopoulos; Andreas G. Veneris (Int. J. Netw. Manag., 2024)

LMPT: A Novel Authenticated Data Structure to Eliminate Storage Bottlenecks for High Performance Blockchains. - Jemin Andrew Choi; Sidi Mohamed Beillahi; Srisht Fateh Singh; Panagiotis Michalopoulos; Peilun Li; Andreas G. Veneris; Fan Long (IEEE Trans. Netw. Serv. Manag., 2024)

Option Contracts in the DeFi Ecosystem: Opportunities, Solutions, and Technical Challenges. - Srisht Fateh Singh; Vladyslav Nekriach; Panagiotis Michalopoulos; Andreas G. Veneris; Jeffrey Klinck (Int. J. Netw. Manag., 2025)

Secure Smart Contract with Control Flow Integrity. - Zhiyang Chen; Sidi Mohamed Beillahi; Pasha Barahimi; Cyrus Minwalla; Han Du; Andreas G. Veneris; Fan Long (CoRR, 2025)

VerifyThisBench: Generating Code, Specifications, and Proofs All at Once. - Xun Deng; Sicheng Zhong; Andreas G. Veneris; Fan Long; Xujie Si (CoRR, 2025)